M61314SP 데이터 시트보기 (PDF) - Renesas Electronics
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M61314SP Datasheet PDF : 10 Pages
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M61314SP
I2C BUS Control Section SDA, SCL Characteristics
Item
Min. input LOW voltage
Max. input HIGH voltage
SCL clock frequency
Time the bus must be free before a new transmission can start
Hold time start condition. After this period the first clock pulse is generated
The LOW period of the clock
The HIGH period of the clock
Set-up time for start condition (Only relevant for a repeated start condition)
Hold time DATA
Set-up time DATA
Rise time of both SDA and SCL lines
Fall time of both SDA and SCL lines
Set-up time for stop condition
Symbol
VIL
VIH
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tr
tf
tSU:STO
Min.
−0.5
3.0
0
1.3
0.6
1.3
0.6
0.6
0
100
20+0.1Cb
20+0.1Cb
0.6
Max.
1.5
5.5
400
0.9
300
300
Unit
V
V
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
Timing Chart
tr, tf
VIH
SDA
VIL
tBUF
tHD: STA
VIH
SCL
VIL
S
tSU: DAT
tHD: DAT
tLOW
tHIGH
tSU: STA
S
tSU: STO
P
S
Rev.2.00 Sep 14, 2006 page 6 of 9
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