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M81019FP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M81019FP
Mitsubishi
MITSUBISHI ELECTRIC  Mitsubishi
M81019FP Datasheet PDF : 10 Pages
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MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
8. ACTIVE MILLER EFFECT CLAMP NMOS OUTPUT TIMING DIAGRAM
The structure of the output driver stage is shown in following figure. This circuit structure employs a solution for the problem
of the Miller current through Cres in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to
increase the safety margin, this circuit structure uses a NMOS to establish a low impedance path to prevent the self-turn-on
due to the parasitic Miller capacitor in power switches.
VIN=0
(from HIN/LIN)
VPG/VN1G
VBS/VCC
P1
Cres
VOUT
N1
Cies
N2
high dv/dt
VN2G
VS/VNO
Active Miller Effect
Clamp NMOS
When HIN/LIN is at low level and the voltage of the VOUT (IGBT gate voltage) is below active Miller effect clamp NMOS
input threshold voltage, the active Miller effect clamp NMOS is being turned on and opens a low resistive path for the Miller
current through Cres.
VIN
VPG
VN1G
VOUT
VN2G
P1 ON
N1 OFF
N2 OFF
P1 OFF
N1 ON
Active Miller effect clamp
NMOS input threshold
P1 ON
N1 OFF
N2 ON
N2 OFF
TW
Active Miller effect clamp NMOS
keeps turn-on if TW does not exceed
active Miller clamp NMOS filter time
Aug. 2009
9

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