MAX16051ETI 데이터 시트보기 (PDF) - Maxim Integrated

부품명

상세내역

제조사

MAX16051ETI

Voltage Monitors/Sequencer Circuits with Reverse-Sequencing Capability

Maxim Integrated 

MAX16050/MAX16051

Voltage Monitors/Sequencer Circuits with

Reverse-Sequencing Capability

Detailed Description

The MAX16050 monitors up to 5 voltages (Figure 1)

with the ability to sequence up to 4 voltages, while the

MAX16051 monitors up to 6 voltages with the ability to

sequence up to 5 voltages. These devices control sys-

tem power-up and power-down in a particular sequence

order. The MAX16050/MAX16051 turn off all supplies

and assert a reset to the processor when any of the volt-

ages falls below its respective threshold. The MAX16050/

MAX16051 offer an 85mA pulldown feature that helps

discharge the output capacitance of DC-DC converters

to ensure timely power-down. In addition, the MAX16050/

MAX16051 also reverse sequence, monitoring each pow-

er-supply output voltage present at the associated DISC_

input and ensuring that the voltage falls below 250mV

before turning off the next supply.

The MAX16050 provides three sequence logic inputs,

which select the sequence order from 24 possible

combinations (Table 1). In the default mode (SEQ1 = SEQ2

= SEQ3 = High Impedance), the power-up sequence is

OUT1→OUT2→OUT3→OUT4. The MAX16051 features

an additional channel and the sequence order is fixed

at OUT1→OUT2→OUT3 →OUT4→OUT5. For complex

systems with a large number of power supplies, the

MAX16050/MAX16051 can be used in a daisy-chain

configuration. Reverse sequencing in the daisy-chained

configuration is still possible.

The MAX16050/MAX16051 keep all OUT_ low (all of the

supplies in the off-state) until four conditions are met.

1) The voltage at ABP exceeds the undervoltage

lockout threshold. See VABP vs. VCC curve in

Typical Operating Characteristics.

2) The voltage at the analog enable input (EN) is

above its threshold.

3) The shutdown input, SHDN, is not asserted.

4) All DISC_ voltages must be below 250mV.

When all of these conditions are met, independent of the

order, the device starts the power-sequencing process

by turning on OUT1–OUT_ in the sequence order. The

sequence delay between each OUT_ is the time required

for the power-supply voltage to exceed the undervolt-

age threshold plus the additional time delay set by the

external delay capacitor; if no capacitor is connected to

the sequence delay timing input (DELAY), only a short

propagation delay (10μs) occurs. As each voltage meets

its respective threshold, the next OUT_ in the sequence

goes high impedance (open-drain output), allowing the

next power supply to turn on, which is then monitored

by the next SET_ input. When all of the voltages exceed

their respective thresholds, the reset output (RESET)

deasserts after a reset timeout period to allow the system

controller to start operating.

During sequenced turn-on, there is no time limit on any

power supply output to come up. The device waits until a

SET_ input goes above its threshold before asserting the

corresponding OUT_ pin high.

After sequencing is complete, if any SET_ input

drops below its threshold, a fault is detected, and all

power supplies are simultaneously turned off by the

OUT_ outputs asserting low_. Additionally, the RESET

output asserts low, the DISC_ current pulls down turn

on, and the FAULT output pulls low for at least 1.9μs.

The MAX16050/MAX16051 will then be ready to power

on again. Sequencing begins as soon as the four startup

conditions are met.

Sequencing

The MAX16050 features three three-state sequence logic

inputs that select one of the 24 possible sequence orders

(Table 1). These inputs allow the sequence order to be

changed even after the board layout is finalized. The

MAX16051 offers five channels and the device powers up

in a fixed order from OUT1 to OUT5.

www.maximintegrated.com

Maxim Integrated │  15

Share Link: