MAX2742 데이터 시트보기 (PDF) - Maxim Integrated
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MAX2742 Datasheet PDF : 8 Pages
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Single-Chip Global Positioning System
Receiver Front-End
Pin Description
PIN
1
2
3, 4, 12, 17, 23,
25, 32, 39, 44, 46
5, 6, 8, 9, 13, 24,
30, 38, 42, 45
7
10
11, 21, 22,
27, 33–36, 40
14
15
16
18
19, 20
26
28
29
31
37
41
43
47, 48
—
NAME
RBIAS
CBIAS
VDD
FUNCTION
External Bias Resistor. Connect a 100kΩ ±1% resistor in parallel with a 0.1µF capacitor in
series with a 71kΩ resistor to GND.
External Bias Capacitor. Connect a 0.1µF capacitor to GND.
Supply Voltage. Bypass to GND with 100pF and 100nF capacitors as close to the pin as
possible with the smaller value capacitor closer to the pin.
GND
Ground. Connect to PC board ground plane.
RFIN
IFSEL
LNA Input. Requires external matching network.
IF Output Select. Selects output type. Drive high for single-ended output, drive low for
differential output.
I.C.
Internally Connected. Leave unconnected.
DCLK
CLKENB2
CLKENB1
AGCFLT
OUT-, OUT+
CLKOUT1
DOUT
CLKOUT2
DIN
SHDN
VTUNE
CPOUT
XTALIN1,
XTALIN2
EP
Digital Control Clock
Clock Output Enable 2. Drive high to enable limited-swing clock output.
Clock Output Enable 1. Drive high to enable full-swing clock output.
AGC External Filter
Differential Comparator Outputs
Full-Swing Clock Output
Digital Output
Limited-Swing Clock Output
Digital-Control Data Input
Shutdown. Drive SHDN low to disable all device functions. Drive SHDN high for normal
operation.
VCO Tuning Input. Connect directly to the loop filter output.
Charge-Pump Output. Connect directly to the loop filter input.
Crystal Oscillator Input. Connect XTALIN1 and XTALIN2 together and to the TCXO output
through a coupling capacitor.
Exposed Paddle. Internally connected to GND. Connect to PC board ground plane for
optimal performance.
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