MAX6850 데이터 시트보기 (PDF) - Maxim Integrated
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MAX6850 Datasheet PDF : 34 Pages
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4-Wire Interfaced, 7-, 14-, and 16-Segment Alpha-
numeric Vacuum-Fluorescent Display Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical operating circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Output Rise and Fall Time
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
tRFT
CLOAD = 100pF
Output High-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOH
ISOURCE = 10 mA
V+ - 0.6
Output Low-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOL
ISINK = 10 mA
Output Short-Circuit Source
Current PHASE1, PHASE2,
PORT0, PORT1, PUMP, VFLOAD,
IOHSC
Output programmed high, output short
circuit to GND (Note 2)
62
VFDOUT, VFCLK, VFBLANK
Output Short-Circuit Sink Current
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
IOLSC
Output programmed low, output short
circuit to V+ (Note 2)
4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (Figure 8)
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
DIN Hold Time
Minimum CS Pulse High
tCP
tCH
tCL
tCSS
tCSH
tDS
tDH
tCSW
DOUT Cascade Setup Time
PORT0, PORT1
tCSU PORT0 and/or PORT1 enabled as DOUT
VFD INTERFACE TIMING CHARACTERISTICS (Figure 11)
VFCLK Clock Period
VFCLK Pulse Width High
VFCLK Pulse Width Low
tVCP
tVCH
tVCL
(Note 2)
(Note 2)
(Note 2)
VFCLK Rise to VFD Load Rise
Hold Time
tVCSH (Note 2)
VFDOUT Setup Time
VFLOAD Pulse High
tVDS
tVCSW
(Note 2)
(Note 2)
72
38.4
19
19
9.5
5
9.5
2
19
9.5
500
250
250
19
50
245
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
MAX UNITS
25
ns
V
0.4
V
125
mA
125
mA
ns
ns
ns
ns
ns
ns
ns
ns
ns
2050
ns
ns
ns
µs
ns
ns
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