MC34923R2 데이터 시트보기 (PDF) - Motorola => Freescale

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MC34923R2

Full-Bridge PWM Motor Driver

Motorola => Freescale 

Freescale Semiconductor, Inc.

D14, Enable Logic

Bit D14, in conjunction with the PWM/ENABLE pin,

determines if the output drivers are in the chopped (OFF) or ON

state.

PWM/

ENABLE

0

1

1

0

D14

Operating

Mode

0

Chopped

1

0

ON

1

D15, Direction Logic

Bit D15, in conjunction with the DIR pin, determines if the

device is operating in the forward or reverse state.

State

DIR

D15 DCMA DCMB

0

Reverse

1

0

Low High

1

1

Forward

0

0

High Low

1

D16, Divisor SPAN Select

Bit D16, in conjunction with the SPAN pin, determines if VREF

is divided by 5 or 10.

Divisor SPAN D16

1

0

÷5

0

1

0

0

÷10

1

1

D17, Internal PWM Mode

Bit D17, in conjunction with the PWMMODE pin, selects

mixed or slow current decay.

PWMMODE

0

1

1

0

D17

Current

Decay Mode

0

Mixed

1

0

Slow

1

D18, Test Mode

Bit D18 low (default) operates the device in normal mode.

D18 is only used for testing purposes. The user should never

change this bit.

D19, Sleep Mode

Bit D19 selects a Sleep mode to minimize power

consumption when not in use. This disables much of the

internal circuitry, including the regulator and charge pump. On

power-up the serial port is initialized to all zeros. Bit D19 should

be programmed high for 1.0 ms before attempting to enable any

output driver.

D19 Sleep Mode

0

Sleep

1

Normal

Serial Port Write Timing Operations

Data is clocked into the shift register on the rising edge of the

CLOCK signal. Normally STROBE will be held high, only

brought low to initiate a write cycle. Refer to Figure 2, Serial Port

Write Timing, page 8, for the minimum timing requirements.

VREG

This internally generated voltage is used to operate the sink-

side outputs. The VREG pin should be decoupled with a 0.22 µF

capacitor to ground. VREG is internally monitored and, in the

case of a fault condition, the outputs of the device are disabled.

Charge Pump

The charge pump is used to generate a gate supply voltage

greater than VBB to drive the source-side gates. A 0.22 µF

ceramic capacitor should be connected between CP1 and CP2

for pumping purposes. A 0.22 µF ceramic capacitor should be

connected between VB and VBB to act as a reservoir to operate

the high-side devices. The VB voltage is internally monitored

and, in the case of a fault condition, the source outputs of the

device are disabled.

Shutdown

In the event of a fault (excessive junction temperature or low

voltage on VB or VREG), the outputs of the device are disabled

until the fault condition is removed. At power-up, and in the

event of low VDD, the Undervoltage Lockout circuit disables the

drivers and resets the data in the serial port to all zeros.

PWM Timer Function

The PWM timer is programmable via the serial port (bits D2–

D10) to provide off-time PWM signals to the control circuitry. In

the mixed current-decay mode, the first portion of the off time

operates in fast decay, until the fast decay time count (serial bits

D7–D10) is reached, followed by slow decay for the rest of the

off-time period (bits D2–D6). If the fast decay time is set longer

than the off time, the device effectively operates in fast decay

mode. Bit D17, in conjunction with PWMMODE, selects mixed

or slow decay.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

34923

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