OM5721 데이터 시트보기 (PDF) - Philips Electronics

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OM5721

STB5660 (Set-Top Box) STB concept

Philips Electronics 

Philips Semiconductors

STB5660 (Set-Top Box) STB concept

Product specification

OM5721

1 FEATURES

1.1 SAA7214 features

1.1.1 GENERAL SAA7214 FEATURES

• Internal PR3001 32-bit RISC processor running at

40.5 MHz

• Comprehensive driver software and development tool

support

• A JTAG interface for board test support

• 1-kbyte data and 4-kbyte instruction caches

(write-through style).

1.1.2 MPEG2 SYSTEMS FEATURES

• Parsing of Transport Stream (TS), Philips

Semiconductors hardware and proprietary software

data streams. Maximum input rate is 108 Mbits/s.

• A Digital Video Broadcasting (DVB) compliant

descrambler core, incorporating storage for up to

6 control word pairs

• Hardware section filtering based on 32 different Packet

Identifiers (PIDs) with a flexible number of filter

conditions (8 or 4-byte condition plus 8 or 4-byte mask)

per PID and a total filter capacity of 40 (8-byte condition

checks) or up to 80 (4-byte condition checks) filter

conditions

• 4 Transport Stream/Packetized Elementary Stream

(PES) filters for retrieval of data at TS or PES level for

applications such as subtitling, TXT or retrieval of

private data

• Flexible Direct Memory Access (DMA) based storage of

the 32 section substreams and 4 TS/PES data

substreams in the external memory

• System time base management with a double counter

mechanism for clock control and discontinuity handling

• 2 Presentation Time Stamp (PTS)/Decoding Time

Stamp (DTS) timers

• A General Purpose/High Speed (GP/HS) filter which can

serve as alternative input from e.g. IEEE 1394 devices.

It can also output either scrambled or descrambled TS

to IEEE 1394 devices.

1.1.3 EXTERNAL INTERFACE FEATURES

• A 16-bit microcontroller extension bus supporting

DRAM, Flash, (E)PROM and external memory mapped

I/O devices. It also supports a synchronous interface to

communicate with the integrated MPEG Audio Video

Graphics (AVG) decoder SAA7215 at 40.5 Mbytes/s.

• An IEEE 1284 interface supporting master and slave

modes. Usable as a general purpose port.

• 3 UART (RS232) data ports with DMA capabilities

(187.5 kbits/s) including hardware flow control signals

RXD, TXD, RTS, CTS for modem support

• Two dedicated smart-card reader interfaces (ISO 7816

compatible) with DMA capabilities

• Two I2C-bus master/slave transceivers supporting the

standard (100 kbits/s) and fast (400 kbits/s) I2C-bus

modes

• 32 general purpose, bidirectional I/O interface pins,

which may also be used as interrupt inputs.

• 2 Pulse Width Modulated (PWM) outputs with 8-bit

resolution.

1.2 SAA7215 features

1.2.1 GENERAL SAA7215 FEATURES

• Single or double external synchronous DRAM organized

as 1M × 16 or 2 × 1M × 16 interfacing at 81 MHz. Due to

efficient memory use in MPEG decoding, more than

1 Mbit is available for graphics in the single SDRAM

configuration whereas 17 Mbits are available in the

double SDRAM configuration targeted to BSkyB 3.00

and Canal+ 4.0 specifications.

• Dedicated input for compressed audio and video in PES

or Elementary Stream (ES) in byte wide or bit serial

format. Accompanying strobe signals distinguish

between audio and video data.

• Optimum compatibility with the SAA7214 Transport

Mega Instructions Per Second (TMIPS) controller

• Flexible memory allocation under control of the external

Central Processing Unit (CPU) enables optimized

partitioning of memory for different tasks.

• Boundary scan testing implemented.

1.2.2 CPU RELATED FEATURES

• External SDRAM self test

• Asynchronous interface possible with external

microcontroller

1999 May 05

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