DIGITAL SIGNAL PROCESSOR FOR CDP
PRELIMINARY
S5L9290X
$94 Command
Control of function modes in DSP
Command Address
D7
D6
D5
Mode control 2
10010100
($94)
MSCK
SW
WDCK
SW
-
Data
D4
D3
D2
-
RFCK
SW
-
D1
D0
-
JTFRV1
Bit
Name
Data = 0 Data = 1
Comment
D7
MSCK_SW
Internal External Input SBCK terminal when input the 1-bit DAC
master clock in external
D6
WDCK_SW
X'tal
VCO2 WDCK frequency selection
D5
-
-
-
-
D4
-
-
-
-
D3
RFCK_SW
MICOM
TESTV Use RFCK clock in CLV sero processing according to
jitter mode
D2
-
-
-
-
D1
-
-
-
-
D0
JTFRV1
X'tal
VCO1 Use VCO1 clock in data processing
19