SC220I5P 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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SC220I5P

XpressFlow Engine XpressFlow 2020 Ethernet Routing Switch Chipset

Zarlink Semiconductor Inc 

PRELIMINARY

XpressFlow-2020 Series –

Ethernet Switch Chipset

INFORMATION

SC220

XpressFlow Engine

1.4 Connection Diagram – 256-BGA Package (Top View)

1

2

3

A

L_A

[13]

L_A

[12]

L_A

[10]

4

5

6

7

L_A[5] / L_A[2] /

P_C[3] P_C[0]

8

9 10 11 12 13 14 15 16 17 18 19 20

C_ C_ EC# C_D C_D C_D C_D C_D P_A P_A P_A P_A P_ P_

MF#

[2] [3] [6] [10] [13] [11] [8] [6] [3] BS16# RDY#

B

L_A

[14]

L_A L_A L_A L_A[3] / C_ CE#

[11] [8] [6] P_C[1]

C_ C_D C_D C_D C_D C_D P_A P_A P_A P_ P_A P_

CM# [1] [4] [7] [11] [14] [10] [7] [4] ADS# [2] INT

C

L_A

[18]

L_A

[16]

L_A

[15]

L_A

[9]

L_A L_A[4] / L_WE C_

[7] P_C[2] [3] WE#

C_

FF#

C_D

[0]

C_D

[5]

C_D

[9]

C_D

[12]

C_D

[15]

P_A

[9]

P_A

[5]

P_A P_ CS# P_ P_RST

[1]

RWC OUT

D

L_OE

[1]#

L_OE

[3]#

L_A

[17]

VDD

(Core)

VSS

VDD

VSS

VDD

VSS

VSS

C_D

[8]

VDD

VSS

VDD

VDD

(Core)

VSS

VDD

P_RST

IN#

P_

CLK

E

L_BWE L_BWE

[2]# [3]#

L_WE

[1]#

VSS

VSS

P_D P_D

[31] [30]

F

L_

ADSC#

L_BWE L_BWE

[0]# [1]#

VDD

VDD

P_D

[29]

P_D

[28]

P_D

[27]

G

L_D

[0]

L_OE

[0]#

VSS

VDD P_D P_D P_D

(Core) [26] [25] [24]

H

L_D

[3]

L_D

[2]

L_D L_WE

[1] [0]#

VSS

P_D

[23]

P_D

[22]

P_D

[21]

J

L_D

[7]

L_D

[6]

L_D

[4]

L_D

[5]

VDD

P_D

[20]

P_D

[19]

P_D

[18]

K

L_D

[9]

L_D

[8]

VDD

VSS

P_D

[17]

P_D

[16]

P_D

[15]

L

L_D

[10]

L_D

[11]

L_D

[12]

VSS

P_D P_D

P_D

[12] [13]

[14]

M

L_D

[13]

L_D

[14]

L_D VDD

[15] (Core)

VSS

P_D

[9]

P_D

[10]

P_D

[11]

N

L_D

[16]

L_D

[17]

L_D

[18]

VSS

P_D P_D P_D P_D

[3] [6] [7] [8]

P

L_D

[19]

L_D

[20]

L_D

[21]

VDD

VDD P_D P_D P_D

(Core) [2] [4] [5]

R

L_D

[22]

L_D

[23]

L_D

[24]

L_D

[26]

VDD

P_D

[0]

P_D

[1]

T

L_D

[25]

L_D

[27]

L_D

[28]

VSS

VSS

S_REQ S_REQ S_GNT

[7]# [8]# [8]#

U

L_D

[29]

L_D

[30]

L_D

[31]

VDD

VSS

S_D

[4]

VSS

VDD

VDD

(Core)

VSS

VDD

VSS

S_D

[25]

S_D S_REQ S_GNT S_GNT S_GNT S_GNT

[29] [1]# [4]# [5]# [6]# [7]#

V

L_WE L_ S_

[2]# CLK TABT#

S_D

[0]

S_D

[3]

S_D

[7]

S_D

[10]

S_D

[13]

VDD

S_D

[20]

S_D

[23]

S_D

[26]

VDD

S_D

[30]

VDD

S_REQ S_REQ

[4]# [5]#

W

L_OE

[2]#

S_MSG

EN#

S_

EOF#

S_

OVLD#

S_D

[1]

S_D

[5]

S_D

[8]

S_D

[11]

S_D

[14]

S_D

[17]

S_D

[19]

S_D

[22]

VSS

S_D

[27]

S_HP S_GNT S_REQ S_GNT

REQ# [1]# [6]# [3]#

Y

T_

MODE

S_ S_

IRDY CLK

S_D S_D S_D S_D S_D S_D S_D S_D S_D

[2] [6] [9] [12] [15] [16] [18] [21] [24]

S_D S_D S_REQ S_GNT S_REQ

[28] [31] [2]# [2]# [3]#

© 1998 Vertex Networks, Inc.

8

1999

Rev. 4.5 – February

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