SST39VF100 데이터 시트보기 (PDF) - Silicon Storage Technology

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SST39VF100

1 Mbit (64K x16) Multi-Purpose Flash

Silicon Storage Technology 

1 Mbit Multi-Purpose Flash

SST39LF100 / SST39VF100

Data Sheet

ADDRESS A15-0

CE#

OE#

WE#

DQ6

TOEH

TCE

TOE

FIGURE 6: TOGGLE BIT TIMING DIAGRAM

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

363 ILL F07.1

ADDRESS A15-0

CE#

SIX-BYTE CODE FOR CHIP-ERASE

5555 2AAA

5555

5555

2AAA

5555

TSCE

OE#

WE#

TWP

DQ15-0

XXAA XX55

XX80

XXAA

XX55

XX10

SW0

SW1

SW2

SW3

SW4

SW5

Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are

interchageable as long as minimum timings are met. (See Table 10)

X can be VIL or VIH, but no other value.

FIGURE 7: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM

363 ILL F08.4

©2001 Silicon Storage Technology, Inc.

11

S71129-02-000 6/01 363

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