VRS700-QLI23 데이터 시트보기 (PDF) - Unspecified
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VRS700-QLI23 Datasheet PDF : 45 Pages
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VRS700
VERSA
Datasheet Rev 1.3
The transistor would be off and the pull-up will maintain
the output at a high level. Also, note that if an external
device with a logical low value is connected to the pin,
the current will flow out of the pin. In order to have a
real bi-directional output, the input should be in a high
impedance state. It is for this reason that we call ports
P1, P2, P3 and P4 “quasi bi-directional”.
Structure of Port 0
The internal structure of P0 is shown in Figure 6. The
auxiliary function of this port requires a particular logic.
As opposed to the other ports, P0 is truly bi-directional.
In other words, when used as an input, it is considered
to be in a floating logical state (high impedance state).
This arises from the absence of the internal pull-up
resistance. The pull-up resistance is actually replaced
by a transistor that is only used when the port is used
to access external memory/data bus (EA=0).
When used as an I/O port, P0 acts as an open drain
port and the use of an external pull-up resistor is likely
to be required for most applications.
FIGURE 6: PORT P0’S PARTICULAR STRUCTURE
Read Register
Address A0/A7
Co ntr ol
Internal Bus
W rite t o
Register
Q
D Flip-Flop
Q
Vcc
X1
IC Pin
Read Pin
When P0 is used as an external memory bus input (for
a MOVX instruction, for example), the outputs of the
register are automatically forced to 1.
Port P0 and P2 as Address and Data Bus
The output stage may receive data from two sources
(Figure 7):
• The outputs of register P0 or the bus address
itself multiplexed with the data bus for P0.
• The outputs of the P2 register or the high part
(A8/A15) of the bus address for the P2 port.
FIGURE 7: P2 PORT STRUCTURE
Read Register
Internal Bus
Write t o
Re gister
A ddress
Q
D Flip-Flop
Q
Co ntr ol
V cc
Pull-u p
Ne two rk
X1
I C Pin
Read P in
When the ports are used as an address or data bus,
the special function registers P0 and P2 are
disconnected from the output stage. The 8 bits of the
P0 register are forced to 1 and the content of the P2
register remains constant.
Auxiliary Port 1 Functions
The port 1 I/O pins are shared with the SPWM outputs,
Timer 2 EXT and T2 input as shown below:
Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Mnemonic
T2
SPWM0
T2EX
SPWM1
SPWM2
SPWM3
SPWM4
SPWM5
SPWM6
SPWM7
Function
Timer 2 counter input
SPWM0 output
Timer2 Auxiliary input
SPWM1 output
SPWM2 output
SPWM3 output
SPWM4output
SPWM5 output
SPWM6 output
SPWM7 output
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