TMP47P201VP 데이터 시트보기 (PDF) - Toshiba

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TMP47P201VP

CMOS 4-bit Microcontroller

Toshiba 

TMP47C101/201

2.4 Data Memory (RAM)

(2) Direct addressing mode

The 47C101 has 64 x 4 bits (addresses 00H through 3FH) of

the data memory (RAM), and the 47C201 has 128 x 4 bits

(addresses 00H through 7FH).

The RAM is addressed in one of the three ways (address-

ing modes):

In this mode, an address is directly specified by the 8

bits of the second byte (operand) in the instruction

field.

Example: LD A, 2CH ; Acc←RAM [2CH]

(1) Register-indirect addressing mode

(3) Zero-page addressing mode

In this mode, a page is specified by the H register and

an address in the page by the L register.

Example: LD A, @HL ; Acc←RAM [HL]

In this mode, an address in zero-page (addresses 00H

through 0FH) is specified by the lower 4 bits of the sec-

ond byte (operand) in the instruction field.

Example: ST #3, 05H ; RAM [05H]←3

Figure 2-5. Addressing Mode

2.4.1 Data Memory Map

Figure 2-6 shows the data memory map. The data memory is

also used for the following special purpose.

ΠStack and Stack Pointer Word (SPW)

 Data Counter (DC)

Ž Count registers of the timer/counters (TC1, TC2)

 Zero-page

Figure 2-6. Data Memory Map (47C201)

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