R5H30211 데이터 시트보기 (PDF) - Renesas Electronics

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R5H30211

Renesas Microcomputer

Renesas Electronics 

R5H30211

CLK

φ

Double of oscillator clock

φ

Same as on-chip oscillator

clock

φ

Half of on-chip oscillator clock

tscyc

tscyc

tscyc

Figure 4.3 System Clock Timing (External clock)

I/O port

(input)

VIH

VIL

tf

VIH

VIL

tr

Figure 5 I/O Port Input Waveform

VCC

CLK

1.8 V

VIH

VIL

0.8V

RES

VIL

ton

tRWL1

VIL

VIL

tRWL2

VIL

tRWL2 toff

Note: At power-on and after power-off, Vcc, CLK, and RES pins should be

driven low (GND level).

Figure 6 Power ON/OFF and RES Input Timing

CLK

(in sleep mode 2)

Sleep mode 2

CLK

(in sleep mode 1)

Sleep mode 1

VIH

IRQ

VIL

VIL

tCLKH

tCLKS tIRQW

Program

execution state

Power-down state

Exception handling state

SLEEP instruction

IRQ

Figure 7 Interrupt Timing in Sleep Mode 1 and Sleep Mode 2

REJ03B0259-0110 Rev.1.10 Jun. 05, 2009

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