ML4821 데이터 시트보기 (PDF) - Fairchild Semiconductor
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ML4821 Datasheet PDF : 12 Pages
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ML4821
Pin Connection
PRODUCT SPECIFICATION
18-Pin PDIP (P18)
ILIM
1
IA OUT
2
IA–
3
IA+
4
ISINE
5
EA OUT
6
EA–
7
VRMS
8
SOFT START
9
18
GND
17
CT
16
VREF
15
VCC
14
OUT
13
PGND
12
RT
11
OVP
10
SYNC
TOP VIEW
ILIM
IA OUT
IA–
IA+
ISINE
EA OUT
EA–
VRMS
SOFT START
N/C
20-Pin SOIC (S20)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
TOP VIEW
GND
CT
VREF
VCC
OUT
PGND
RT
OVP
SYNC
N/C
Pin Description
Pin Number
18-Pin DIP 20-Pin SOIC Name
Function
1
1
ILIM Peak cycle-by-cycle current limit input
2
2
IA OUT Output and compensation node of the average current error amplifier
3
3
IA– Inverting input of the average current error amplifier
4
4
IA+ Non-Inverting input of the average current error amplifier and output of the
gain modulator
5
5
ISINE Gain modulator input
6
6
EA OUT Output of output voltage error amplifier
7
7
INV Inverting input to error amplifier
8
8
VRMS Input for average line voltage compensation
9
9
SOFT Normally connected to soft start capacitor
START
10
12
SYNC Oscillator synchronization input
11
13
OVP Inhibits output pulses when the voltage at this pin exceeds 5V. Also,
when the voltage at this pin is less than 0.7V, the IC goes into low current
shut-down mode.
12
14
RT Timing resistor for the oscillator
13
15
PWR Return for the high current totem pole output
GND
14
16
OUT High current totem pole output
15
17
VCC Positive supply for the IC
16
18
VREF Buffered output for the 5V voltage reference
17
19
CT Timing capacitor for the oscillator.
18
20
GND Analog signal ground
2
REV. 1.0.2 6/19/01
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