AD8317ACHIPS 데이터 시트보기 (PDF) - Analog Devices
부품명
상세내역
제조사
AD8317ACHIPS Datasheet PDF : 20 Pages
| |||
AD8317
USING THE AD8317
BASIC CONNECTIONS
The AD8317 is specified for operation up to 10 GHz; as a result,
low impedance supply pins with adequate isolation between
functions are essential. A power supply voltage of between 3.0 V
and 5.5 V should be applied to VPOS. Power supply decoupling
capacitors of 100 pF and 0.1 μF should be connected close to
this power supply pin.
VS (3.0V TO 5.5V)
C5
0.1µF R2
C4 0Ω
100pF
C2
1
SIGNAL
INPUT
R1
52.3Ω
47nF
C1
8
INLO
INHI
1
7
6
VPOS TADJ
AD8317
COMM CLPF
2
3
5
VOUT
VSET
4
47nF
2
VOUT
R4
0Ω
1SEE THE TEMPERATURE COMPENSATION OF OUTPUT VOLTAGE SECTION.
2SEE THE OUTPUT FILTERING SECTION.
Figure 22. Basic Connections
The paddle of the LFCSP package is internally connected to
COMM. For optimum thermal and electrical performance, the
paddle should be soldered to a low impedance ground plane.
INPUT SIGNAL COUPLING
The RF input (INHI) is single-ended and must be ac-coupled.
INLO (input common) should be ac-coupled to ground.
Suggested coupling capacitors are 47 nF ceramic 0402-style
capacitors for input frequencies of 1 MHz to 10 GHz. The
coupling capacitors should be mounted close to the INHI and
INLO pins. The coupling capacitor values can be increased to
lower the high-pass cutoff frequency of the input stage. The
high-pass corner is set by the input coupling capacitors and the
internal 10 pF high-pass capacitor. The dc voltage on INHI and
INLO is approximately one diode voltage drop below VPOS.
VPOS
5pF
CURRENT
5pF
18.7kΩ
INHI
INLO
18.7kΩ
FIRST
GAIN
STAGE
2kΩ A = 9dB
gm
STAGE
Figure 23. Input Interface
OFFSET
COMP
Figure 22) combines with the relatively high input impedance to
give an adequate broadband 50 Ω match.
The coupling time constant, 50 × CC/2, forms a high-pass
corner with a 3 dB attenuation at fHP = 1/(2π × 50 × CC ), where
C1 = C2 = CC. Using the typical value of 47 nF, this high-pass
corner is ~68 kHz. In high frequency applications, fHP should be
as large as possible to minimize the coupling of unwanted low
frequency signals. In low frequency applications, a simple RC
network forming a low-pass filter should be added at the input
for similar reasons. This low-pass filter network should generally
be placed at the generator side of the coupling capacitors, thereby
lowering the required capacitance value for a given high-pass
corner frequency.
OUTPUT INTERFACE
The VOUT pin is driven by a PNP output stage. An internal
10 Ω resistor is placed in series with the output and the VOUT
pin. The rise time of the output is limited mainly by the slew
on CLPF. The fall time is an RC-limited slew given by the load
capacitance and the pull-down resistance at VOUT. There is an
internal pull-down resistor of 1.6 kΩ. A resistive load at VOUT
is placed in parallel with the internal pull-down resistor to
provide additional discharge current.
VPOS
CLPF
+
0.8V
–
10Ω
VOUT
1200Ω
COMM
400Ω
Figure 24. Output Interface
To reduce the fall time, VOUT should be loaded with a resistive
load of <1.6 kΩ. For example, with an external load of 150 Ω,
the AD8317 fall time is <7 ns.
SETPOINT INTERFACE
The VSET input drives the high impedance (40 kΩ) input of an
internal op amp. The VSET voltage appears across the internal
1.5 kΩ resistor to generate ISET. When a portion of VOUT is
applied to VSET, the feedback loop forces
−ID × log10(VIN/VINTERCEPT) = ISET
(2)
If VSET = VOUT/2x, then ISET = VOUT/(2x × 1.5 kΩ).
The result is
VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT)
VSET
20kΩ VSET
ISET
While the input can be reactively matched, in general, this is not
necessary. An external 52.3 Ω shunt resistor (connected on the
signal side of the input coupling capacitors, as shown in
Rev. B | Page 11 of 20
20kΩ
1.5kΩ
COMM
COMM
Figure 25. VSET Interface
Share Link: 