AD5735 데이터 시트보기 (PDF) - Analog Devices
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AD5735 Datasheet PDF : 49 Pages
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Data Sheet
AD5735
TIMING CHARACTERISTICS
AVDD = VBOOST_x = 15 V; AVSS = −15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND =
GNDSWx = 0 V; REFIN = 5 V; voltage outputs: RL = 1 kΩ, CL = 220 pF; current outputs: RL = 300 Ω; all specifications TMIN to TMAX,
unless otherwise noted.
Table 3.
Parameter1, 2, 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
Limit at TMIN, TMAX
33
13
13
13
13
198
5
5
5
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
µs min
5
10
500
See Table 2
10
5
40
5
500
800
µs min
ns min
ns max
µs max
ns min
µs max
ns max
µs min
ns min
ns min
20
µs min
5
µs min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th/32nd SCLK falling edge to SYNC rising edge (see Figure 77)
SYNC high time after a configuration write
SYNC high time after a DAC update write
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (applies to any channel that has digital slew
rate control enabled; single DAC updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLEAR high time
CLEAR activation time
SCLK rising edge to SDO valid
SYNC rising edge to DAC output response time (LDAC = 0) (Single DAC updated)
LDAC falling edge to SYNC rising edge
RESET pulse width
SYNC high to next SYNC low (Single DAC updated)
Digital slew rate control enabled
Digital slew rate control disabled
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 3, Figure 4, Figure 6, and Figure 7.
Rev. E | Page 9 of 49
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