MX25L1606EM1I-12G 데이터 시트보기 (PDF) - Macronix International

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MX25L1606EM1I-12G

8M-BIT / 16M-BIT [x 1 / x 2] CMOS SERIAL FLASH

Macronix International 

MX25L8006E

MX25L1606E

Contents

FEATURES................................................................................................................................................................... 5

GENERAL DESCRIPTION.......................................................................................................................................... 6

PIN CONFIGURATIONS .............................................................................................................................................. 7

PIN DESCRIPTION....................................................................................................................................................... 7

BLOCK DIAGRAM....................................................................................................................................................... 8

MEMORY ORGANIZATION.......................................................................................................................................... 9

Table 1-1. Memory Organization (8Mb)............................................................................................................... 9

Table 1-2. Memory Organization (16Mb)............................................................................................................. 9

DEVICE OPERATION................................................................................................................................................. 10

Figure 1. Serial Modes Supported....................................................................................................... 10

DATA PROTECTION.................................................................................................................................................. 11

Table 2. Protected Area Sizes............................................................................................................................. 12

Table 3. 512 bit Secured OTP Definition............................................................................................................ 13

HOLD FEATURES...................................................................................................................................................... 14

Figure 2. Hold Condition Operation ........................................................................................................ 14

COMMAND DESCRIPTION....................................................................................................................................... 15

Table 4. COMMAND DEFINITION...................................................................................................................... 15

(1) Write Enable (WREN).................................................................................................................................... 16

(2) Write Disable (WRDI).................................................................................................................................... 16

(3) Read Status Register (RDSR)....................................................................................................................... 16

(4) Write Status Register (WRSR)...................................................................................................................... 17

Table 5. Protection Modes.................................................................................................................................. 18

(5) Read Data Bytes (READ).............................................................................................................................. 19

(6) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 19

(7) Dual Output Mode (DREAD)......................................................................................................................... 19

(8) Sector Erase (SE).......................................................................................................................................... 19

(9) Block Erase (BE)........................................................................................................................................... 20

(10) Chip Erase (CE).......................................................................................................................................... 20

(11) Page Program (PP)..................................................................................................................................... 20

(12) Deep Power-down (DP)............................................................................................................................... 21

(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES) .............................................. 21

(14) Read Identification (RDID)........................................................................................................................... 22

(15) Read Electronic Manufacturer ID & Device ID (REMS)............................................................................... 22

Table 6. ID DEFINITIONS .................................................................................................................................. 22

(16) Enter Secured OTP (ENSO)........................................................................................................................ 22

(17) Exit Secured OTP (EXSO).......................................................................................................................... 22

(18) Read Security Register (RDSCUR)............................................................................................................. 23

Table 7. SECURITY REGISTER DEFINITION................................................................................................... 23

P/N: PM1548

REV. 1.2, JUL. 02, 2010

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