MFRC52201HN1 데이터 시트보기 (PDF) - NXP Semiconductors.

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MFRC52201HN1

Standard performance MIFARE and NTAG frontend

NXP Semiconductors. 

NXP Semiconductors

MFRC522

Standard performance MIFARE and NTAG frontend

8.1.3.3 UART framing

Table 11.

Bit

Start

Data

Stop

UART framing

Length

1-bit

8 bits

1-bit

Value

0

data

1

Remark: The LSB for data and address bytes must be sent first. No parity bit is used

during transmission.

Read data: To read data using the UART interface, the flow shown in Table 12 must be

used. The first byte sent defines both the mode and the address.

Table 12. Read data byte order

Pin

Byte 0

RX (pin 24)

address

TX (pin 31)

-

Byte 1

-

data 0

ADDRESS

RX

SA A0 A1 A2 A3 A4 A5 (1) R/W SO

DATA

TX

SA D0 D1 D2 D3 D4 D5 D6 D7 SO

MX

DTRQ

(1) Reserved.

Fig 9. UART read data timing diagram

001aak588

Write data: To write data to the MFRC522 using the UART interface, the structure shown

in Table 13 must be used.

The first byte sent defines both the mode and the address.

MFRC522

Product data sheet

COMPANY PUBLIC

All information provided in this document is subject to legal disclaimers.

Rev. 3.9 — 27 April 2016

112139

© NXP Semiconductors N.V. 2016. All rights reserved.

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