MFRC52201HN1 데이터 시트보기 (PDF) - NXP Semiconductors.

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MFRC52201HN1

Standard performance MIFARE and NTAG frontend

NXP Semiconductors. 

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ADDRESS

RX

SA A0 A1 A2 A3 A4 A5 (1) R/W SO

DATA

SA D0 D1 D2 D3 D4 D5 D6 D7 SO

ADDRESS

TX

SA A0 A1 A2 A3 A4 A5 (1) R/W SO

MX

DTRQ

(1) Reserved.

Fig 10. UART write data timing diagram

001aak589

Remark: The data byte can be sent directly after the address byte on pin RX.

Address byte: The address byte has to meet the following format:

The MSB of the first byte sets the mode used. To read data from the MFRC522, the MSB is set to logic 1. To write data to the

MFRC522 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 14.

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