MMA8451Q_12 데이터 시트보기 (PDF) - Freescale Semiconductor
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MMA8451Q_12 Datasheet PDF : 52 Pages
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2.3
I2C Interface Characteristic
Table 4. I2C Slave Timing Values(1)
Parameter
SCL Clock Frequency
Pullup = 4.7 kΩ, Cb = 20 pF
Pullup = 4.7 kΩ, Cb = 40 pF
Pullup = 4.7 kΩ, Cb = 400 pF
Pullup = 1 kΩ, Cb = 20 pF
Pullup = 1 kΩ, Cb = 400 pF
Symbol
fSCL
I2C Fast Mode
Min
Max
0
2.250
0
100
0
Nonfunctional
0
4.50
0
750
Unit
MHz
kHz
—
MHz
kHz
Bus Free Time between STOP and START Condition
Repeated START Hold Time
Repeated START Setup Time
STOP Condition Setup Time
SDA Data Hold Time(2)
SDA Valid Time (4)
SDA Valid Acknowledge Time (5)
SDA Setup Time
SCL Clock Low Time
SCL Clock High Time
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;DAT
tVD;ACK
tSU;DAT
tLOW
tHIGH
1.3
0.6
0.6
0.6
0.5
100(6)
4.7
4
μs
μs
μs
μs
0.9(3)
μs
0.9(3)
μs
0.9(3)
μs
ns
μs
μs
SDA and SCL Rise Time
SDA and SCL Fall Time (7) (8)
tr
1000
ns
tf
300
ns
Pulse width of spikes on SDA and SCL that must be suppressed by input filter
tSP
50
ns
1. All values referred to VIH (min) and VIL (max) levels.
2. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
3. The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard mode and Fast mode, but must be less than the maximum of tVD;DAT or tVD;ACK
by a transition time.
4. tVD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
5. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
6. A Fast mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the
SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C
specification) before the SCL line is released. Also the acknowledge timing must meet this setup time
7. Cb = total capacitance of one bus line in pF.
8. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.
This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified tf.
handbook, full pagewidth
SDA
tf
tLOW
tr
tSU;DAT
tf
tHD;STA
SCL
S
tHD;STA
tHD;DAT
tHIGH
tSU;STA
Sr
Figure 5. I2C Slave Timing Diagram
tSP
tr
tBUF
tSU;STO
P
S
MSC610
MMA8451Q
8
Sensors
Freescale Semiconductor, Inc.
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