MAX6722 데이터 시트보기 (PDF) - Maxim Integrated

부품명

상세내역

제조사

MAX6722

Dual/Triple Ultra-Low-Voltage SOT23 µP Supervisory Circuits

Maxim Integrated 

Dual/Triple Ultra-Low-Voltage SOT23 µP

Supervisory Circuits

Pin Description (continued)

PIN

MAX6715/ MAX6717/

MAX6716 MAX6718

MAX6719/

MAX6720

MAX6721/

MAX6722

MAX6723/

MAX6724

MAX6725/

MAX6726

MAX6727

MAX6728/ NAME

MAX6729

FUNCTION

—

—

—

—

—

—

—

Active-Low Power-Fail

Monitor Output, Open-

Drain or Push-Pull. PFO is

asserted low when PFI is

less than 0.626V. PFO

4

PFO deasserts without a reset

timeout period. Open-

drain outputs require an

external pullup resistor.

Push-pull outputs are

referenced to VCC1.

Active-High Reset

Output, Open-Drain or

Push-Pull. RST changes

from low to high when

VCC1 or VCC2 drops

below selected reset

thresholds, RSTIN is

below threshold, MR is

pulled low, or the

watchdog triggers a

—

—

—

—

—

4

—

—

RST

reset. RST remains HIGH

for the reset timeout

period after VCC1/

VCC 2/RSTIN exceed the

device reset thresholds,

MR goes low to high, or

the watchdog triggers a

reset. Open-drain outputs

require an external pullup

resistor. Push-pull

outputs are referenced to

VCC1.

Detailed Description

Supply Voltages

The MAX6715–MAX6729 microprocessor (µP) supervi-

sory circuits maintain system integrity by alerting the µP

to fault conditions. These ICs are optimized for systems

that monitor two or three supply voltages. The output-

reset state is guaranteed to remain valid while either

VCC1 or VCC2 is above 0.8V.

Threshold Levels

Input voltage threshold level combinations are indicat-

ed by a two-letter code in the Reset Voltage Threshold

Suffix Guide (Table 1). Contact factory for availability of

other voltage threshold combinations.

Reset Outputs

The MAX6715–MAX6729 provides an active-low reset

output (RST) and the MAX6725/MAX6726 provides

both an active-high (RST) and an active-low reset out-

put (RST). RST, RST, RST1, and RST2 are asserted

when the voltage at either VCC1 or VCC2 falls below the

voltage threshold level, RSTIN drops below threshold,

or MR is pulled low. Once reset is asserted it stays low

for the reset timeout period (see Table 2). If VCC1,

VCC2, or RSTIN goes below the reset threshold before

the reset timeout period is completed, the internal timer

_______________________________________________________________________________________ 9

Share Link: