S3C6410 데이터 시트보기 (PDF) - Samsung

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S3C6410

RISC Microprocessor

Samsung 

Table of Contents (Continued)

Chapter 3

System Controller

3.3.4 Phase Locked Loop (PLL) ...............................................................................................................3-4

3.3.4.1 Clock selection between PLLs and input reference clock ........................................................3-5

3.3.4.2 ARM and AXI/AHB/APB bus clock generation .........................................................................3-6

3.3.4.3 MFC clock generation...............................................................................................................3-7

3.3.4.4 Camera I/F clock generation ....................................................................................................3-8

3.3.4.5 Clock generation for display (POST, LCD, and scaler)............................................................3-8

3.3.4.6 Clock generation for audio (IIS and PCM)................................................................................3-8

3.3.4.7 Clock generation for UART, SPI, and MMC .............................................................................3-9

3.3.4.8 Clock generation for IrDA, USB host........................................................................................3-10

3.3.4.9 Clock ON/OFF control ..............................................................................................................3-10

3.3.4.10 Clock output............................................................................................................................3-10

3.3.5 Synchronous 667MHz operating mode ...........................................................................................3-10

3.3.5.1 Clock divider structure ..............................................................................................................3-10

3.3.5.2 Transition to synchronous 667MHz operating mode................................................................3-11

3.3.5.3 Limitation of synchronous 667MHz operating mode ................................................................3-12

3.3.6 Low Power Mode Operation ............................................................................................................3-12

3.3.6.1 Power domain in S3C6410X ....................................................................................................3-13

3.3.6.2 NORMAL/IDLE mode ...............................................................................................................3-13

3.3.6.3 STOP mode ..............................................................................................................................3-14

3.3.6.4 DEEP-STOP mode ...................................................................................................................3-15

3.3.6.5 SLEEP mode ............................................................................................................................3-15

3.3.6.6 Wakeup.....................................................................................................................................3-17

3.3.6.7 Reset ..........................................................htt.p://ww.w.Da.taShe.et4U.n.et/ .........................................................................3-17

3.3.6.8 Hardware reset .........................................................................................................................3-17

3.3.6.9 Watchdog reset.........................................................................................................................3-18

3.3.6.10 Wakeup reset..........................................................................................................................3-19

3.3.7 misceleneous. ..................................................................................................................................3-19

3.4 register description ..................................................................................................................................3-20

3.4.1 Memory map ....................................................................................................................................3-20

3.4.2 individual register descriptions.........................................................................................................3-22

3.4.2.1 PLL Control Registers ..............................................................................................................3-22

3.4.2.2 Clock source control register ....................................................................................................3-27

3.4.2.3 Clock divider control register ....................................................................................................3-29

3.4.2.4 Clock output configuration register...........................................................................................3-31

3.4.2.5 Clock gating control register .....................................................................................................3-32

3.4.2.6 AHB bus control register...........................................................................................................3-36

3.4.2.7 Secure DMA control register ....................................................................................................3-40

3.4.2.8 System ID register ....................................................................................................................3-41

3.4.2.9 System Others register.............................................................................................................3-41

3.4.2.10 Memory controller status register ...........................................................................................3-42

3.4.2.11 Power mode control register...................................................................................................3-46

3.4.2.12 System stabilization counter...................................................................................................3-49

3.4.2.13 Cacheable bus transaction selection register ........................................................................3-50

3.4.2.14 Others control register ............................................................................................................3-51

3.4.2.15 Status register.........................................................................................................................3-53

3.4.2.16 Information register.................................................................................................................3-54

vi

S3C6410X_USER’S MANUAL_REV 1.00

datasheet pdf - http://www.DataSheet4U.net/

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