MT4LC1M16E5TG-5S 데이터 시트보기 (PDF) - Micron Technology

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MT4LC1M16E5TG-5S

16Mb: 1 MEG x16 EDO DRAM

Micron Technology 

NOTES

1. All voltages referenced to VSS.

2. The minimum specifications are used only to

indicate cycle time at which proper operation over

the full temperature range (0ºC £ TA £ 70ºC for

commercial) and (-20ºC £ TA £ 80ºC for extended)

is ensured.

3. An initial pause of 100µs is required after power-

up, followed by eight RAS# refresh cycles (RAS#-

ONLY or CBR with WE# HIGH), before proper

device operation is ensured. The eight RAS# cycle

wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

4. NC pins are assumed to be left floating and are

not tested for leakage.

5. ICC is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time and the outputs open.

6. Column address changed once each cycle.

7. Enables on-chip refresh and address counters.

8. This parameter is sampled. VDD = +3.3V; f = 1 MHz.

9. AC characteristics assume tT = 2.5ns.

10.VIH (MIN) and VIL (MAX) are reference levels for

measuring timing of input signals. Transition

times are measured between VIH and VIL (or

between VIL and VIH).

11.In addition to meeting the transition rate

specification, all input signals must transit

between VIH and VIL (or between VIL and VIH) in a

monotonic manner.

12.Measured with a load equivalent to two TTL gates

and 100pF; and VOL = 0.8V and VOH = 2V.

13.tWCS, tRWD, tAWD, and tCWD are not restrictive

operating parameters. tWCS applies to EARLY

WRITE cycles. tRWD, tAWD and tCWD apply to

READ-MODIFY-WRITE cycles. If tWCS tWCS

(MIN), the cycle is an EARLY WRITE cycle and the

data output will remain an open circuit through-

out the entire cycle. If tWCS < tWCS (MIN) and

tRWD tRWD (MIN), tAWD tAWD (MIN) and

tCWD tCWD (MIN), the cycle is a READ-

MODIFY-WRITE and the data output will contain

data read from the selected cell. If neither of the

above conditions is met, the state of data-out is

indeterminate. OE# held HIGH and WE# taken

LOW after CAS# goes LOW results in a LATE

WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD

and tAWD are not applicable in a LATE WRITE

cycle.

14.Assumes that tRCD tRCD (MAX).

16Mb: 1 MEG x16

EDO DRAM

15.If CAS# is LOW at the falling edge of RAS#, Q will

be maintained from the previous cycle. To initiate

a new cycle and clear the data-out buffer, CAS#

must be pulsed HIGH for tCP.

16.These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading

edge in LATE WRITE or READ-MODIFY-WRITE

cycles.

17.If OE# is tied permanently LOW, LATE WRITE, or

READ-MODIFY-WRITE operations are not

permissible and should not be attempted.

Additionally, WE# must be pulsed during CAS#

HIGH time in order to place I/O buffers in High-Z.

18.LATE WRITE and READ-MODIFY-WRITE cycles

must have both tOD and tOEH met (OE# HIGH

during WRITE cycle) in order to ensure that the

output buffers will be open during the WRITE

cycle. The DQs will provide the previously read

data if CAS# remains LOW and OE# is taken back

LOW after tOEH is met. If CAS# goes HIGH prior to

OE# going back LOW, the DQs will remain open.

19.Assumes that tRCD < tRCD (MAX). If tRCD is

greater than the maximum recommended value

shown in this table, tRAC will increase by the

amount that tRCD exceeds the value shown.

20.tOFF (MAX) defines the time at which the output

achieves the open circuit condition and is not

referenced to VOH or VOL. It is referenced from the

rising edge of RAS# or CAS#, whichever occurs last.

21.The tRAD (MAX) limit is no longer specified. tRAD

(MAX) was specified as a reference point only. If

tRAD was greater than the specified tRAD (MAX)

limit, then access time was controlled exclusively

by tAA (tRAC and tCAC no longer applied). With or

without the tRAD (MAX) limit, tAA, tRAC, and tCAC

must always be met.

22.The tRCD (MAX) limit is no longer specified. tRCD

(MAX) was specified as a reference point only. If

tRCD was greater than the specified tRCD (MAX)

limit, then access time was controlled exclusively

by tCAC (tRAC [MIN] no longer applied). With or

without the tRCD limit, tAA and tCAC must always

be met.

23.Either tRCH or tRRH must be satisfied for a READ

cycle.

24.The first CAS#x edge to transition LOW.

25.Output parameter (DQx) is referenced to corre-

sponding CAS# input; DQ0-DQ7 by CASL# and

DQ8-DQ15 by CASH#.

1 Meg x 16 EDO DRAM

D52_B.p65 – Rev. B; Pub. 3/01

10

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc

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