MT4C1M16E5TG-5 데이터 시트보기 (PDF) - Micron Technology

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MT4C1M16E5TG-5

16Mb: 1 MEG x16 EDO DRAM

Micron Technology 

NOTES (continued)

26.Each CAS#x must meet minimum pulse width.

27.The last CAS#x edge to transition HIGH.

28.Last falling CAS#x edge to first rising CAS#x edge.

29.Last rising CAS#x edge to first falling CAS#x edge.

30.Last rising CAS#x edge to next cycle’s last rising

CAS#x edge.

16Mb: 1 MEG x16

EDO DRAM

31.Last CAS#x to go LOW.

32.A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# is LOW and

OE# is HIGH.

1 Meg x 16 EDO DRAM

D52_B.p65 – Rev. B; Pub. 3/01

11

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc

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