MT4C1M16E5TG-6 데이터 시트보기 (PDF) - Micron Technology

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MT4C1M16E5TG-6

16Mb: 1 MEG x16 EDO DRAM

Micron Technology 

GENERAL DESCRIPTION (continued)

of the two signals results in a BYTE WRITE cycle. CASL#

transitioning LOW selects an access cycle for the lower

byte (DQ0-DQ7), and CASH# transitioning LOW se-

lects an access cycle for the upper byte (DQ8-DQ15).

Each bit is uniquely addressed through the 20 ad-

dress bits during READ or WRITE cycles. These are

entered 10 bits (A0-A9) at a time. RAS# is used to latch

the first 10 bits and CAS#, the latter 10 bits. The CAS#

function also determines whether the cycle will be a

refresh cycle (RAS# ONLY) or an active cycle (READ,

WRITE or READ-WRITE) once RAS# goes LOW.

The CASL# and CASH# inputs internally generate a

CAS# signal that functions like the single CAS# input

on other DRAMs. The key difference is each CAS# input

(CASL# and CASH#) controls its corresponding eight

DQ inputs during WRITE accesses. CASL# controls

DQ0-DQ7, and CASH# controls DQ8-DQ15. The two

CAS# controls give the 1 Meg x 16 both BYTE READ and

BYTE WRITE cycle capabilities.

16Mb: 1 MEG x16

EDO DRAM

A logic HIGH on WE# dictates read mode, while a

logic LOW on WE# dictates write mode. During a WRITE

cycle, data-in (D) is latched by the falling edge of WE or

CAS# (CASL# or CASH#), whichever occurs last. An

EARLY WRITE occurs when WE is taken LOW prior to

either CAS# falling. A LATE WRITE or READ-MODIFY-

WRITE occurs when WE falls after CAS# (CASL# or

CASH#) was taken LOW. During EARLY WRITE cycles,

the data outputs (Q) will remain High-Z, regardless of

the state of OE#. During LATE WRITE or READ-

MODIFY-WRITE cycles, OE# must be taken HIGH to

disable the data outputs prior to applying input data.

If a LATE WRITE or READ-MODIFY-WRITE is attempted

while keeping OE# LOW, no WRITE will occur, and the

data outputs will drive read data from the accessed

location.

The 16 data inputs and 16 data outputs are routed

through 16 pins using common I/O. Pin direction is

controlled by OE# and WE#.

The 1 Meg x 16 DRAM must be refreshed periodi-

cally in order to retain stored data.

RAS#

V IH

V IL

CASL#/CASH#

V

V

IH

IL

ADDR VVIIHL

ROW

COLUMN (A)

COLUMN (B)

COLUMN (C)

COLUMN (D)

DQ

V

V

IOH

IOL

OE# VVIIHL

OPEN

VALID DATA (A)

tOD

tOES

tOE

VALID DATA (A)

VALID DATA (B)

tOD

tOEHC

VALID DATA (C)

tOD

tOEP

VALID DATA (D)

The DQs go back to

Low-Z if tOES is met.

The DQs remain High-Z

until the next CAS# cycle

if tOEHC is met.

Figure 1

OE# Control of DQs

The DQs remain High-Z

until the next CAS# cycle

if tOEP is met.

DON’T CARE

UNDEFINED

1 Meg x 16 EDO DRAM

D52_B.p65 – Rev. B; Pub. 3/01

2

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc

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