MT28F800B5WG-8BET 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT28F800B5WG-8BET

FLASH MEMORY

Micron Technology 

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

COMMAND SET

To simplify writing of the memory blocks, the

MT28F800B5 and MT28F008B5 incorporate an ISM

that controls all internal algorithms for writing and

erasing the floating gate memory cells. An 8-bit com-

mand set is used to control the device. Details on how

to sequence commands are provided in the Command

Execution section. Table 1 lists the valid commands.

ISM STATUS REGISTER

The 8-bit ISM status register (see Table 2) is polled

to check for WRITE or ERASE completion or any

related errors. During or following a WRITE, ERASE or

ERASE SUSPEND, a READ operation outputs the status

register contents on DQ0–DQ7 without prior com-

mand. While the status register contents are read, the

outputs are not updated if there is a change in the ISM

status unless OE# or CE# is toggled. If the device is not

in the write, erase, erase suspend or status register read

mode, READ STATUS REGISTER (70h) can be issued to

view the status register contents.

All of the defined bits are set by the ISM, but only

the ISM and erase suspend status bits are reset by the

ISM. The erase, write and VPP status bits must be

cleared using CLEAR STATUS REGISTER. If the VPP sta-

tus bit (SR3) is set, the CEL does not allow further write

or erase operations until the status register is cleared.

This enables the user to choose when to poll and clear

the status register. For example, the host system may

perform multiple BYTE WRITE operations before

checking the status register instead of checking after

each individual WRITE. Asserting the RP# signal or

powering down the device also clears the status regis-

ter.

Table 2: Status Register

STATUS

BIT #

SR7

SR6

SR5

SR4

SR3

STATUS REGISTER BIT

ISM STATUS

1 = Ready

0 = Busy

ERASE SUSPEND STATUS

1 = ERASE suspended

0 = ERASE in progress/completed

ERASE STATUS

1 = BLOCK ERASE error

0 = Successful BLOCK ERASE

WRITE STATUS

1 = WORD/BYTE WRITE error

0 = Successful WORD/BYTE WRITE

VPP STATUS

1 = No VPP voltage detected

0 = VPP present

SR0-2 RESERVED

DESCRIPTION

The ISMS bit displays the active status of the state machine during

WRITE or BLOCK ERASE operations. The controlling logic polls this bit

to determine when the erase and write status bits are valid.

Issuing an ERASE SUSPEND places the ISM in the suspend mode and

sets this and the ISMS bit to “1.” The ESS bit remains “1” until an

ERASE RESUME is issued.

ES is set to “1” after the maximum number of ERASE cycles is executed

by the ISM without a successful verify. ES is only cleared by a CLEAR

STATUS REGISTER command or after a RESET.

WS is set to “1” after the maximum number of WRITE cycles is

executed by the ISM without a successful verify. WS is only cleared by a

CLEAR STATUS REGISTER command or after a RESET.

VPPS detects the presence of a VPP voltage. It does not monitor VPP

continuously, nor does it indicate a valid VPP voltage. The VPP pin is

sampled for 5V after WRITE or ERASE CONFIRM is given. VPPS must be

cleared by CLEAR STATUS REGISTER or by a RESET.

Reserved for future use.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

11Micron Technology, Inc. Reserves the right to change products or specifications without notice.

©2002, Micron Technology Inc.

Share Link: