MT28F800B5SG-8B 데이터 시트보기 (PDF) - Micron Technology
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MT28F800B5SG-8B Datasheet PDF : 30 Pages
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8Mb
SMART 5 BOOT BLOCK FLASH MEMORY
tional error information is set in three other bits: VPP
status, write status, and erase status.
Command Execution Cell (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register
or status register). Commands may be issued to the
CEL while the ISM is active. However, there are restric-
tions on what commands are allowed in this condition.
See the Command Execution section for more detail.
ERASE function is block-oriented. All READ and
WRITE operations are done on a random-access basis.
The boot block is protected from unintentional
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP#
or that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining ten blocks do not require that either of
these two conditions be met before WRITE or ERASE
operations.
Deep Power-Down Mode
To allow for maximum power conservation, the
MT28F800B5 and MT28F008B5 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to VSS ±0.2V. In this mode, the current
draw is a maximum of 20µA. Entering deep power-
down also clears the status register and sets the ISM to
the read array mode.
MEMORY ARCHITECTURE
The MT28F800B5 and MT28F008B5 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into eleven addressable blocks that vary in size
and are independently erasable. When blocks rather
than the entire array are erased, total device endur-
ance is enhanced, as is system flexibility. Only the
Boot Block
The hardware-protected boot block provides extra
security for the most sensitive portions of the firm-
ware. This 16KB block may only be erased or written
when the RP# pin is at the specified boot block unlock
voltage (VHH) or when the WP# pin is HIGH. During a
WRITE or ERASE of the boot block, the RP# pin must
be held at VHH or the WP# pin held HIGH until the
WRITE or ERASE is completed. (The WP# pin does not
apply to the SOP package.) The VPP pin must be at
VPPH (5V) when the boot block is written to or erased.
The MT28F800B5 and MT28F008B5 are available in
two configurations and top or bottom boot block. The
top boot block version supports processors of the x86
variety. The bottom boot block version is intended for
680X0 and RISC applications. Figure 1 illustrates the
memory address maps associated with these two ver-
sions.
Figure 1: Memory Address Maps
Bottom Boot
MT28F800B5/008B5xx-xxB
Top Boot
MT28F800B5/008B5xx-xxT
WORD ADDRESS
7FFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
BYTE ADDRESS
FFFFFh
E0000h
DFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
80000h
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
8KB Parameter Block
8KB Parameter Block
16KB Boot Block
8Mb Smart 5 Boot Block Flash Memory
MT28F800B5_3.fm - Rev. 3, Pub. 8/2002
WORD ADDRESS
7FFFFh
7E000h
7DFFFh
7D000h
7CFFFh
7C000h
7BFFFh
70000h
6FFFFh
60000h
5FFFFh
50000h
4FFFFh
40000h
3FFFFh
30000h
2FFFFh
20000h
1FFFFh
10000h
0FFFFh
00000h
BYTE ADDRESS
FFFFFh
FC000h
FBFFFh
FA000h
F9FFFh
F8000h
F7FFFh
E0000h
DFFFFh
C0000h
BFFFFh
A0000h
9FFFFh
80000h
7FFFFh
60000h
5FFFFh
40000h
3FFFFh
20000h
1FFFFh
00000h
16KB Boot Block
8KB Parameter Block
8KB Parameter Block
96KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
8Micron Technology, Inc. Reserves the right to change products or specifications without notice.
©2002, Micron Technology Inc.
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