MT28F800B5WG-8BET 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT28F800B5WG-8BET

FLASH MEMORY

Micron Technology 

8Mb

SMART 5 BOOT BLOCK FLASH MEMORY

Parameter Blocks

The two 8KB parameter blocks store less sensitive

and more frequently changing system parameters and

also may store configuration or diagnostic coding.

These blocks are enabled for erasure when the VPP pin

is at VPPH. No super-voltage unlock or WP# control is

required.

Main Memory Blocks

The eight remaining blocks are general-purpose

memory blocks and do not require a super-voltage on

RP# or WP# control to be erased or written. These

blocks are intended for code storage, ROM-resident

applications or operating systems that require in-sys-

tem update capability.

OUTPUT (READ) OPERATIONS

The MT28F800B5 and MT28F008B5 feature three

different types of READs. Depending on the current

mode of the device, a READ operation produces data

from the memory array, status register or device iden-

tification register. In each of these three cases, the

WE#, CE# and OE# inputs are controlled in a similar

manner. Moving between modes to perform a specific

READ is described in the Command Execution section.

Memory Array

To read the memory array, WE# must be HIGH, and

OE# and CE# must be LOW. Valid data is output on the

DQ pins when these conditions are met, and a valid

address is given. Valid data remains on the DQ pins

until the address changes, or OE# or CE# goes HIGH,

whichever occurs first. The DQ pins continue to out-

put new data after each address transition as long as

OE# and CE# remain LOW.

The MT28F800B5 features selectable bus widths.

When the memory array is accessed as a 512K x 16,

BYTE# is HIGH, and data is output on DQ0–DQ15. To

access the memory array as a 1 Meg x 8, BYTE# must

be LOW, DQ8–DQ14 are High-Z, and all data is output

on DQ0–DQ7. The DQ15/(A-1) pin becomes the lowest

order address input so that 1,048,576 locations can be

read.

After power-up or RESET, the device is automati-

cally in the array read mode. All commands and their

operations are described in the Command Set and

Command Execution sections.

Status Register

Performing a READ of the status register requires

the same input sequencing as a READ of the array

except that the address inputs are “Don’t Care.” The

status register contents are always output on DQ0–

DQ7, regardless of the condition of BYTE# on the

MT28F800B5. DQ8–DQ15 are LOW when BYTE# is

HIGH, and DQ8–DQ14 are High-Z when BYTE# is

LOW. Data from the status register is latched on the

falling edge of OE# or CE#, whichever occurs last. If the

contents of the status register change during a read of

the status register, either OE# or CE# may be toggled

while the other is held LOW to update the output.

Following a WRITE or ERASE, the device automati-

cally enters the status register read mode. In addition,

a READ during a WRITE or ERASE produces the status

register contents on DQ0–DQ7. When the device is in

the erase suspend mode, a READ operation produces

the status register contents until another command is

issued. In certain other modes, READ STATUS REGIS-

TER may be given to return to the status register read

mode. All commands and their operations are

described in the Command Set and Command Execu-

tion sections.

Identification Register

A READ of the two 8-bit device identification regis-

ters requires the same input sequencing as a READ of

the array. WE# must be HIGH, and OE# and CE# must

be LOW. However, ID register data is output only on

DQ0–DQ7, regardless of the condition of BYTE# on the

MT28F800B5. A0 is used to decode between the two

bytes of the device ID register; all other address inputs

are “Don’t Care.” When A0 is LOW, the manufacturer

compatibility ID is output, and when A0 is HIGH, the

device ID is output. DQ8–DQ15 are High-Z when

BYTE# is LOW. When BYTE# is HIGH, DQ8–DQ15 are

00h when the manufacturer compatibility ID is read

and 88h when the device ID is read.

To get to the identification register read mode,

READ IDENTIFICATION may be issued while the

device is in certain other modes. In addition, the iden-

tification register read mode can be reached by apply-

ing a super-voltage (VID) to the A9 pin. Using this

method, the ID register can be read while the device is

in any mode. When A9 is returned to VIL or VIH, the

device will return to the previous mode.

8Mb Smart 5 Boot Block Flash Memory

MT28F800B5_3.fm - Rev. 3, Pub. 8/2002

9Micron Technology, Inc. Reserves the right to change products or specifications without notice.

©2002, Micron Technology Inc.

Share Link: