DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

1402I 데이터 시트보기 (PDF) - Linear Technology

부품명
상세내역
제조사
1402I Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LTC1402
PIN FUNCTIONS
GAIN (Pin 7): Tie to AGND2 to set the reference voltage to
4.096V or tie to VREF to set the reference voltage to 2.048V.
(Note 4)
BIP/UNI (Pin 8): Tie to logic low to set the input range to
unipolar mode or tie to logic high to set the input range to
bipolar mode. (Note 4)
OGND (Pin 9): Output Ground for the Output Driver. This
pin can be tied to the digital ground of the system. All other
ground pins should be tied to the analog ground plane.
DOUT (Pin 10): Three-State Data Output. (Note 3) Each
output data word represents the analog input at the start
of the previous conversion.
OVDD (Pin 11): Output Data Driver Power. Tie to VDD when
driving 5V logic. Tie to 3V when driving 3V logic.
DVDD (Pin 12): Digital Power for Internal Logic. Bypass to
DGND with 10µF ceramic (or 10µF tantalum in parallel with
0.1µF ceramic).
DGND (Pin 13): Digital Ground for Internal Logic. Tie to
solid analog ground plane.
VSS (Pin 14): Negative Supply Voltage. Bypass to solid
analog ground plane with 10µF ceramic (or 10µF tantalum
in parallel with 0.1µF ceramic) or tie directly to the solid
analog ground plane for single supply use. Must be set
more negative than either AIN+ or AIN . Set to 0V or – 5V.
SCK (Pin 15): External Clock. Advances the conversion
process and sequences the output data at DOUT on the
rising edge. Responds to 5V or 3V CMOS and to TTL levels.
(Note 4). One or more pulses wake from Nap or Sleep.
CONV (Pin 16): Holds the input analog signal and starts
the conversion on the rising edge. Responds to 5V or 3V
CMOS and to TTL levels. (Note 4). Two pulses with SCK in
fixed high or fixed low state start Nap Mode. Four pulses
with SCK in fixed high or fixed low state start Sleep mode.
BLOCK DIAGRA
AIN+ 3
AIN– 4
2.048V REF
7 64k
GAIN
5
VREF
6
AGND2
2
AGND1
13
DGND
+
REF AMP
64k
INTERNAL
CLOCK
CSAMPLE
CSAMPLE
12-BIT CAPACITIVE DAC
SUCCESSIVE APPROXIMATION
REGISTER
CONTROL LOGIC
16
CONV
15
SCK
ZEROING SWITCHES
1
12 AVDD
DVDD
14
VSS
+
COMP
OUTPUT
DRIVER
8
BIP/UNI
10
DOUT
11
OVDD
9
OGND
1402 BD
8

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]