HT12D-18 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT12D-18

212 Series of Decoders

Holtek Semiconductor 

HT12D/HT12F

Functional Description

Operation

The 212 series of decoders provides various combina-

tions of addresses and data pins in different packages

so as to pair with the 212 series of encoders.

The decoders receive data that are transmitted by an

encoder and interpret the first N bits of code period as

addresses and the last 12-N bits as data, where N is the

address code number. A signal on the DIN pin activates

the oscillator which in turn decodes the incoming ad-

dress and data. The decoders will then check the re-

ceived address three times continuously. If the received

address codes all match the contents of the decoder¢s

local address, the 12-N bits of data are decoded to acti-

vate the output pins and the VT pin is set high to indicate

a valid transmission. This will last unless the address

code is incorrect or no signal is received.

The output of the VT pin is high only when the transmis-

sion is valid. Otherwise it is always low.

Output type

Of the 212 series of decoders, the HT12F has no data

output pin but its VT pin can be used as a momentary

data output. The HT12D, on the other hand, provides 4

latch type data pins whose data remain unchanged until

new data are received.

Part Data Address Output Operating

No. Pins Pins

Type

Voltage

HT12D 4

8

Latch 2.4V~12V

HT12F 0

12

¾

2.4V~12V

Flowchart

The oscillator is disabled in the standby state and acti-

vated when a logic ²high² signal applies to the DIN pin.

That is to say, the DIN should be kept low if there is no

signal input.

P ow eron

S ta n d b y m o d e

No

C o d e in ?

Y es

D is a b le V T &

ig n o r e th e r e s t o f

th is w o r d

A d d r e s s b its

No

m a tc h e d ?

Y es

S to re d a ta

M a tc h

p r e v io u s s to r e d

No

d a ta ?

Y es

No

3 tim e s

o f c h e c k in g

c o m p le te d ?

Y es

L a tc h d a ta

to o u tp u t &

a c tiv a te V T

No

A d d re s s o r

d a ta e rro r ?

Y es

Decoder timing

E ncoder

T r a n s m is s io n

E n a b le

E ncoder

DOUT

D ecoder V T

L a tc h e d

D a ta O u t

< 1 w o rd

4 w o rd s

check

2 1 4 c lo c k s

T r a n s m itte d

C o n tin u o u s ly

check

4 w o rd s

2 1 4 c lo c k s

Rev. 1.10

4

November 18, 2002

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