AB28F400BR-T80 데이터 시트보기 (PDF) - Intel
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AB28F400BR-T80 Datasheet PDF : 36 Pages
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A28F200BR
Savings (APS) feature which minimizes system
battery current drain, allowing for very low power
designs. To provide even greater power savings,
the boot block family includes a deep power-down
mode which minimizes power consumption by
turning most of the flash memory’s circuitry off.
This mode is controlled by the RP# pin and its
usage is discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during
system reset and power-up/down sequences.
Also, when the flash memory powers-up, it
automatically defaults to the read array mode, but
during a warm system reset, where power
continues uniterrupted to the system components,
the flash memory could remain in a non-read
mode, such as erase. Consequently, the system
Reset pin should be tied to RP# to reset the
memory to normal read mode upon activation of
the Reset pin.
The byte-wide or word-wide input/output is
controlled by the BYTE# pin. See Table 1 for a
detailed description of BYTE# operations,
especially the usage of the DQ15/A-1 pin.
The 28F200 products are available in a
ROM/EPROM-compatible pinout and housed in
the 44-lead PSOP (Plastic Small Outline)
package.
Refer to the DC Characteristics Table, Section 5.2
for complete current and voltage specifications.
Refer to the AC Characteristics Table, Section
5.3, for read, program and erase performance
specifications.
1.3 Applications
The 2-Mbit boot block flash memory family
combines high-density, low-power, high-
performance, cost-effective flash memories with
blocking and hardware protection capabilities.
Their flexibility and versatility reduce costs
throughout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing
system inventory and costs, and eliminating
component handling during the production phase.
E
When the product is in the end-user’s hands, and
updates or feature enhancements become
necessary or mandatory, flash memory eliminates
the need to replace an assembly. The update can
be performed as part of routine maintenance
operation by relatively unsophisticated
technicians.
The reliability of such a field upgrade is enhanced
by a hardware-protected 16-Kbyte boot block. If
the protection methods are implemented in the
circuit design, the boot block will be
unchangeable. Locating the boot-strap code in this
area assures a fail-safe recovery from an update
operation that failed to complete correctly.
The two 8-Kbyte parameter blocks allow
modification of control algorithms to reflect
changes in the process or device being controlled.
A variety of software algorithms allow these two
blocks to behave like a standard EEPROM.
Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a single flash device.
The boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in place, decreasing RAM
requirements.
1.4 Pinouts
Intel’s SmartVoltage boot block architecture
provides upgrade paths in every package pinout to
the 8-Mbit density. The 28F200 44-lead PSOP
pinout follows the industry standard ROM/EPROM
pinout as shown in Figure 2.
Pinouts for the corresponding 4-Mbit and 8-Mbit
components are also provided for convenient
reference. 2-Mbit pinouts are given on the chip
illustration in the center, with 2-Mbit and 8-Mbit
pinouts going outward from the center.
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