24C128C 데이터 시트보기 (PDF) - Atmel Corporation
부품명
상세내역
제조사
24C128C Datasheet PDF : 23 Pages
| |||
7. Device Addressing
The 128K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a
read or write operation. The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all 2-wire EEPROM devices.
Table 7-1. Device Address Byte
Package
SOIC, TSSOP, UDFN,
XDFN, VFBGA
Device Type Identifier
Bit 7
Bit 6
Bit 5
Bit 4
1
0
1
0
Hardware Slave Address Bits Read/ Write
Bit 3
Bit 2
Bit 1
Bit 0
A2
A1
A0
R/W
WLCSP
1
0
1
0
0
0
1
R/W
The next three bits are the A2, A1, and A0 device address bits to allow as many as eight devices on the same
bus. These bits must compare to their corresponding hard wired input pins. The A2, A1, and A0 pins use an
internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
When using the WLCSP package, the A2, A1, and A0 signals are not accessible. The A2 and A1 pins are left
floating, and the previously mentioned automatic pull-down circuit will set these signals to a Logic 0 state. The
A0 signal is internally connected to VCC. As a result, to properly communicate with the device in the WLCSP
package, the A2 and A1 software bits must always be set to a Logic 0, and the A0 software bit must be set to
Logic 1 for any operation. This requirement has been shown in Table 7-1.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device
will return to a standby state.
Data Security: AT24C128C has a hardware data protection scheme that allows the user to write protect the
whole memory when the WP pin is at VCC.
AT24C128C [DATASHEET]
9
Atmel-8734D-SEEPROM-AT24C128C-Datasheet_082015
Share Link: 