MC145201 데이터 시트보기 (PDF) - Motorola => Freescale
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MC145201 Datasheet PDF : 23 Pages
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VPD
Positive Power Supply (Pin 5)
This pin supplies power to both phase/frequency detectors
A and B. The voltage applied on this pin must be no less than
the potential applied to the VDD pin. The maximum voltage
can be + 9.5 V with respect to the GND pin for the MC145200
and + 5.5 V for the MC145201.
For optimum performance, VPD should be bypassed to
GND using a low–inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND
Ground (Pin 7)
Common ground.
100 ns MINIMUM
ENB
CLK
1
2
3
4
5
Din
1
2
3
4
5
1
2
3
4
5
NOTE: It may not be convenient to control the ENB or CLK pins during power up per the Pin Descriptions. If this is the case, the part may
be initialized through the serial port as shown in the figure above. The sequence is similar to accessing the registers except that the
CLK must remain high at least 100 ns after ENB is brought high. Note that 3 groups of 5 bits are needed.
Figure 13. Initializing the PLL through the Serial Port
MC145200
t t Nominal PDout Spurious Current vs fR Frequency
(1 V PDout VPD – 1V)
fR
(kHz)
Current
(RMS nA)
10
1.6
20
5.3
50
22
100
95
200
320
MC145201
t t Nominal PDout Spurious Current vs fR Frequency
(1 V PDout VPD – 1V)
fR
(kHz)
Current
(RMS nA)
10
3.6
20
4.6
50
17
100
75
200
244
NOTE: For information on spurious current measurement see AN1253/D, “An Improved PLL Design Method Without ωn and ζ”.
Table 2. PDout Current, C1 = Low with OUTPUT A NOT
Selected as “Port”; Also, Default Mode When
OUTPUT A Selected as “Port”
C3
C2
PDout Current
0
0
70%
0
1
80%
1
0
90%
1
1
100%
Table 3. PDout Current, C1 = High with OUTPUT A NOT
Selected as “Port”
C3
C2
PDout Current
0
0
25%
0
1
50%
1
0
75%
1
1
100%
MOTOROLA
MC145200•MC145201
11
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