24LC41A 데이터 시트보기 (PDF) - Microchip Technology
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24LC41A Datasheet PDF : 18 Pages
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24LC41A
TABLE 1-2: AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS PORTS)
DDC Monitor Port (Bidirectional mode) and Microcontroller Access Port
Parameter
Symbol
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode
Units
Remarks
Min Max Min Max
Clock frequency (DSCL and FCLK
—
100
—
400 kHz
MSCL)
Clock high time (DSCL and THIGH 4000 —
600
—
ns
MSCL)
Clock low time (DSCL and TLOW 4700
—
1300
—
ns
MSCL)
DSCL, DSDA, MSCL &
MSDA rise time
TR
— 1000 —
300
ns (Note 1)
DSCL, DSDA, MSCL &
MSDA fall time
TF
—
300
—
300
ns (Note 1)
Start condition hold time THD:STA 4000 —
600
—
ns After this period the first clock
pulse is generated
Start condition setup time TSU:STA 4700 —
600
—
ns Only relevant for repeated
Start condition
Data input hold time
THD:DAT 0
—
0
—
ns (Note 2)
Data input setup time
TSU:DAT 250
—
100
—
ns
Stop condition setup time TSU:STO 4000 —
600
—
ns
Output valid from clock
TAA
— 3500 —
900
ns (Note 2)
Bus free time
TBUF 4700
—
1300
—
ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
min to VIL max
TOF
—
250 20 + .1 250
ns (Note 1), CB ≤ 100 pF
CB
Input filter spike suppres-
TSP
—
50
—
50
ns (Note 3)
sion (DSCL, DSDA, MSCL
& MSDA pins)
Write cycle time
TWR
—
10
—
10
ms Byte or Page mode
Endurance
—
1M
—
1M
— cycles 25°C, Vcc = 5.0V, Block mode
(Note 4)
DDC Monitor Port Transmit-only mode Parameters
Output valid from VCLK
TVAA
— 2000
—
1000 ns
VCLK high time
TVHIGH 4000
—
600
—
ns
VCLK low time
TVLOW 4700
—
1300
—
ns
VCLK setup time
TVHST
0
—
0
—
ns
VCLK hold time
TSPVL 4000
—
600
—
ns
Mode transition time
TVHZ
—
500
—
500
ns
Transmit-only power-up
TVPU
0
—
0
—
ns
time
Input filter spike
suppression (VCLK pin)
TSPV
—
100
—
100
ns
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of Start or Stop
conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained at www.microchip.com.
2003 Microchip Technology Inc.
DS21176D-page 3
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