M29F040-120K5TR 데이터 시트보기 (PDF) - STMicroelectronics

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M29F040-120K5TR

4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory

STMicroelectronics 

M29F040

Memory Blocks

The memory blocks of the M29F040 are shown in

Figure 3. The memory array is divided in 8 uniform

blocks of 64 Kbytes. Each block can be erased

separately or any combination of blocks can be

erased simultaneously. The Block Erase operation

is managed automatically by the P/E.C. The opera-

tion can be suspended in order to read from any

other block, and then resumed.

Block Protection provides additional data security.

Each uniform block can be separately protected or

unprotected against Program or Erase. Bringing A9

and G to VID initiates protection, while bringing A9,

G and E to VID cancels the protection. The block

affected during protection is addressed by the in-

puts on A16, A17, and A18. Unprotect operation

affects all blocks.

Operations

Operations are defined as specific bus cycles and

signals which allow Memory Read, Command

Write, Output Disable, Standby, Read Status Bits,

Block Protect/Unprotect, Block Protection Check

and Electronic Signature Read. They are shown in

Tables 3, 4, 5.

Read. Read operations are used to output the

contents of the Memory Array, the Status Register

or the Electronic Signature. Both Chip Enable E

and Output Enable G must be low in order to read

the output of the memory. The Chip Enable input

also provides power control and should be used for

device selection. Output Enable should be used to

gate data onto the output independent of the device

selection. The data read depends on the previous

command written to the memory (see instructions

RST and RSIG, and Status Bits).

Write. Write operations are used to give Instruction

Commands to the memory or to latch input data to

be programmed. A write operation is initiated when

Chip Enable E is Low and Write Enable W is Low

with Output Enable G High. Addresses are latched

on the falling edge of W or E whichever occurs last.

Commands and Input Data are latched on the rising

edge of W or E whichever occurs first.

Output Disable. The data outputs are high imped-

ance when the Output Enable G is High with Write

Enable W High.

Standby. The memory is in standby when Chip

Enable E is High and Program/Erase Controller

P/E.C. is Idle. The power consumption is reduced

to the standby level and the outputs are high im-

pedance, independent of the Output Enable G or

Write Enable W inputs.

Automatic Standby. After 150ns of inactivity and

when CMOS levels are driving the addresses, the

chip automatically enters a pseudo standby mode

where consumption is reduced to the CMOS

standby value, while outputs are still driving the

bus.

Electronic Signature. Two codes identifying the

manufacturer and the device can be read from the

memory, the manufacturer’s code for STMicroelec-

tronics is 20h, and the device code is E2h for the

M29F040. These codes allow programming equip-

ment or applications to automatically match their

interface to the characteristics of the particular

manufacturer’s product. The Electronic Signature

is output by a Read operation when the voltage

applied to A9 is at VID and address inputs A1 and

A6 are at Low. The manufacturer code is output

when the Address input A0 is Low and the device

code when this input is High. Other Address inputs

are ignored. The codes are output on DQ0-DQ7.

This is shown in Table 4.

The Electronic Signature can also be read, without

raising A9 to VID by giving the memory the instruc-

tion RSIG (see below).

Block Protection. Each uniform block can be

separately protected against Program or Erase.

Block Protection provides additional data security,

as it disables all program or erase operations. This

mode is activated when both A9 and G are set to

VID and the block address is applied on A16-A18.

Block Protection is programmed using a Presto F

program like algorithm. Protection is initiated on the

edge of W falling to VIL. Then after a delay of 100µs,

the edge of W rising to VIH ends the protection

operation. Protection verify is achieved by bringing

G, E and A6 to VIL while W is at VIH and A9 at VID.

Under these conditions, reading the data output will

yield 01h if the block defined by the inputs on

A16-A18 is protected. Any attempt to program or

erase a protected block will be ignored by the

device.

Any protected block can be unprotected to allow

updating of bit contents. All blocks must be pro-

tected before an unprotect operation. Block Un-

protect is activated when A9, G and E are at VID.

The addresses inputs A6, A12, A16 must be main-

tained at VIH. Block Unprotect is performed through

a Presto F Erase like algorithm. Unprotect is initi-

ated by the edge of W falling to VIL. After a delay

of 10ms, the edge of W rising to VIH will end the

unprotection operation. Unprotect verify is

achieved by bringing G and E to VIL while A6 and

W are at VIH and A9 at VID. In these conditions,

reading the output data will yield 00h if the block

defined by the inputs on A16-A18 has been suc-

cessfully unprotected. All combinations of A16-

A18 must be addressed in order to ensure that all

of the 8 uniform blocks have been unprotected.

Block Protection Status is shown in Table 5.

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