VSC8161 데이터 시트보기 (PDF) - Vitesse Semiconductor

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VSC8161

2.488Gb/s SONET / SDH 16:1 Mux with Clock Generator and Laser Driver

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8161

2.488Gb/s SONET / SDH

16:1 Mux with Clock Generator and Laser Driver

Figure 2: Single-ended AC-Coupling for REFCK+, REFCK– Inputs

Chip Boundary

VCC = GND

ZO

CIN REFCK+

-1.32V

-1.32V

RT = ZO

VTT

CSE

REFCK-

R| | = 1kΩ (Min.)

VTT

VTT = -2V

CIN TYP = 0.1µF

CSE TYP = 0.1µF for single ended applications. (Capacitor values are

selected for REFCK = 155.52 MHz)

A differential input buffer is used to supply the reference clock to the clock multiplier. Internal biasing will

position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can

either be DC-coupled or AC-coupled; it can also be driven single-ended or differentially. Figure 2 shows the

configuration for single-ended, AC-coupled operation. In the case of direct coupled and single-ended input, it is

recommended that a stable VREF for ECL levels be used for the complementary input if the input common mode

voltage is not -1.32V.

Parity

Systems employing internal parity are supported by the VSC8161. A parity check is performed between the

PARITY input and the 16 data bits. Even parity is expected. In other words, the DINVALID output is the XOR

of all 16 parallel data bits and the PARITY input. If the Exclusive-OR gate fails to confirm even parity, the DIN-

VALID output will be asserted. DINVALID becomes available tDV after the falling edge of CLK16. DINVALID

is a NRZ pulse that is updated every 6.4 ns, i.e., the period of CLK16. The timing relationship of DINVALID to

CLK16 is shown in Figure 6.

The DINVALID pins may be left open if parity is unused.

Laser Driver

The laser driver contained in the VSC8161 provides up to 50mA of DC bias current and 60 mA of modula-

tion current. Direct control of the laser bias and modulation current is provided. Laser bias and modulation cur-

rent levels are monitored and controlled using external components.

A schematic representation of the laser driver output stage showing the relationship between the the exter-

nal controls signals and the internal circuitry is provided in Figure 3.

G52208-0, Rev.2.1

8/28/98

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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