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TA16L1FAA

TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

TA16-Type 2.5 Gbits/s Transponder with

16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Data Sheet

March 2001

Pin Descriptions (continued)

Table 1. TA16-Type Transponder Pinout (continued)

Pin # Pin Name I/O

Logic

Description

86

TxD14P

I

LVPECL Transmitter 155 Mbits/s Data Input

87

TxD14N

I

LVPECL Transmitter 155 Mbits/s Data Input

88

TxDGND

I

SUPPLY Transmitter Digital Ground

89

TxD12P

I

LVPECL Transmitter 155 Mbits/s Data Input

90

TxD12N

I

LVPECL Transmitter 155 Mbits/s Data Input

91

TxD10P

I

LVPECL Transmitter 155 Mbits/s Data Input

92

TxD10N

I

LVPECL Transmitter 155 Mbits/s Data Input

93

TxDGND

I

Supply Transmitter Digital Ground

94

TxD08P

I

LVPECL Transmitter 155 Mbits/s Data Input

95

TxD08N

I

LVPECL Transmitter 155 Mbits/s Data Input

96

TxD06P

I

LVPECL Transmitter 155 Mbits/s Data Input

97

TxD06N

I

LVPECL Transmitter 155 Mbits/s Data Input

98

TxDGND

I

Supply Transmitter Digital Ground

99

TxD04P

I

LVPECL Transmitter 155 Mbits/s Data Input

100

TxD04N

I

LVPECL Transmitter 155 Mbits/s Data Input

101

TxD02P

I

LVPECL Transmitter 155 Mbits/s Data Input

102

TxD02N

I

LVPECL Transmitter 155 Mbits/s Data Input

103

TxDGND

I

Supply Transmitter Digital Ground

104

TxD00P

I

LVPECL Transmitter 155 Mbits/s LSB Data Input

105

TxD00N

I

LVPECL Transmitter 155 Mbits/s LSB Data Input

106

TxDGND

I

Supply Transmitter Digital Ground

107

PCLKP

O LVPECL Transmitter Parallel Reference Clock Output

108

PCLKN

O LVPECL Transmitter Parallel Reference Clock Output

109

TxDGND

I

Supply Transmitter Digital Ground

110

TxAGND

I

Supply Transmitter Analog Ground

111

Tx3.3D

I

Supply Transmitter Digital 3.3 V Supply

112

Tx3.3A

I

Supply Transmitter Analog 3.3 V Supply

113

NC

—

—

No User Connection Permitted

114

PHINIT

I

LVPECL Phase Initialization

115

TXDIS

I

TTL Transmitter Disable

116

NC

—

—

No User Connection Permitted

117

PHERR

O LVPECL Phase Error

118

LLOOP

I

LVTTL Line Loopback (active-low)

119

LOS

O

LVTTL Loss of Signal

120

RxDGND

I

Supply Receiver Digital Ground

121

OOF

I

LVTTL Out of Frame (enable frame detection)

122

RxDGND

I

Supply Receiver Digital Ground

123

Rx3.3D

I

Supply Receiver Digital 3.3 V Supply

124

Rx3.3D

I

Supply Receiver Digital 3.3 V Supply

125

SEARCH

O

LVTTL Frame Search Output

126

RxAGND

I

Supply Receiver Analog Ground

127

RxAGND

I

Supply Receiver Analog Ground

128

Rx3.3A

I

Supply Receiver Analog 3.3 V Supply

1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).

8

Agere Systems Inc.

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