MAX3876E/D 데이터 시트보기 (PDF) - Maxim Integrated

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MAX3876E/D

2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC

Maxim Integrated 

2.5Gbps, Low-Power, +3.3V

Clock Recovery and Data Retiming IC

Pin Description (continued)

PIN

NAME

FUNCTION

19

SCLKO+ Positive Serial Clock Output, CML, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+.

22

SDO-

Negative Data Output, CML, 2.488Gbps

23

SDO+ Positive Data Output, CML, 2.488Gbps

25

LOL

Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor)

30

FIL-

Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

31

FIL+

Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.

SIS

FIL+ FIL-

SDI+

SDI-

SLBI+

SLBI-

AMP

MUX

AMP

MAX3876

PHASE AND

FREQUENCY

DETECTOR

LOOP

FILTER

DQ

CK

I

VCO Q

SDO+

CML

SDO-

SCLKO+

SCLKO-

CML

LOL

TTL

Figure 3. Functional Diagram

Detailed Description

The MAX3876 consists of a fully integrated phase-

locked loop (PLL), input amplifier, data retiming block,

and CML output buffer (Figure 3). The PLL consists of

a phase/frequency detector (PFD), a loop filter, and a

voltage-controlled oscillator (VCO).

This device is designed to deliver the best combination

of jitter performance and power dissipation by using a

fully differential signal architecture and low-noise

design techniques.

Input Amplifier

Input amplifiers are implemented for both the main data

and system loopback inputs. These amplifiers accept

DC-coupled differential input amplitudes from 50mVp-p

up to 1000mVp-p. With AC-coupling, differential input

signal amplitudes can be increased to a maximum of

1600mVp-p. The bit error rate is better than 1 · 10-10 for

input signals as small as 10mVp-p, though the jitter tol-

erance performance will be degraded. For interfacing

with PECL signal levels, see Applications Information.

Phase Detector

The phase detector incorporated in the MAX3876 pro-

duces a voltage proportional to the phase difference

between the incoming data and the internal clock.

Because of its feedback nature, the PLL drives the

error voltage to zero, aligning the recovered clock to

the center of the incoming data eye for retiming.

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