MT28C3212P2FL-10B 데이터 시트보기 (PDF) - Micron Technology

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MT28C3212P2FL-10B

FLASH AND SRAM COMBO MEMORY

Micron Technology 

2 MEG x 16 PAGE FLASH

128K x 16 SRAM COMBO MEMORY

Table 6

Command Descriptions (continued)

CODE DEVICE MODE

D0h Erase Confirm

Program/Erase

Resume

FFh Read Array

01h Lock Block

2Fh Lock Down

D0h Unlock Block

00h Invalid/Reserved

BUS CYCLE

DESCRIPTION

First

If the previous command was an ERASE SETUP command, then the

CSM closes the address and data latches, and it begins erasing the

block indicated on the address pins. During programming/erase, the

device responds only to the READ STATUS REGISTER, PROGRAM

SUSPEND, or ERASE SUSPEND commands and outputs status register

data on the falling edge of F_OE# or F_CE#, whichever occurs last.

First

If a PROGRAM or ERASE operation was previously suspended, this

command resumes the operation.

First

During the array mode, array data is output on the data bus.

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM latches the address and locks the block indicated on the

address bus.

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM latches the address and locks down the block indicated on

the address bus.

Second

If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM latches the address and unlocks the block indicated on the

address bus. If the block had been previously set to lock down, this

operation has no effect.

Unassigned command that should not be used.

2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory

MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02

14

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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