MT28C3212P2FL-11TET 데이터 시트보기 (PDF) - Micron Technology
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MT28C3212P2FL-11TET Datasheet PDF : 47 Pages
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
TRUTH TABLE – FLASH
MODES
Read
Write
Standby
Output Disable
Reset
FLASH SIGNALS
SRAM SIGNALS
MEMORY OUPUT
F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# MEMORY DQ0–DQ15
BUS CONTROL
H
L
L
H
H
L
H
L
H
H
X
X
H
L
H
H
L
X
X
X
SRAM must be High-Z
SRAM any mode allowable
Flash
Flash
Other
Other
Other
DOUT
DIN
High-Z
High-Z
High-Z
NOTES
1, 2, 3
1
4
4, 5
4, 6
TRUTH TABLE – SRAM
MODES
Read
DQ0–DQ15
DQ0–DQ7
DQ8–DQ15
Write
DQ0–DQ15
DQ0–DQ7
DQ8–DQ15
Standby
Output Disable
FLASH SIGNALS
SRAM SIGNALS
MEMORY OUPUT
F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# MEMORY DQ0–DQ15
BUS CONTROL
Flash must be High-Z
L
H
L
H
L
L
L
H
L
H
H
L
L
H
L
H
L
H
L
H
H
L
L
L
L
H
H
L
H
L
L
H
H
L
L
H
H
X
X
X
X
X
Flash any mode allowable X
L
X
X
X
X
L
H
X
X
X
X
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
Other
Other
Other
DOUT
DOUT LB
DOUT UB
DIN
DIN LB
DIN UB
High-Z
High-Z
High-Z
NOTES
1, 3
7
8
1, 3
9
10
4
4
4
NOTE: 1. Two devices may not drive the memory bus at the same time.
2. Allowable flash read modes include read array, read query, read configuration, and read status.
3. Outputs are dependent on a separate device controlling bus outputs.
4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.
5. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.
6. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to
control the bus outputs at a time.
7. Data output on lower byte only; upper byte High-Z.
8. Data output on upper byte only; lower byte High-Z.
9. Data input on lower byte only.
10. Data input on upper byte only.
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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