AT28LV010-20 데이터 시트보기 (PDF) - Atmel Corporation

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AT28LV010-20

1-Megabit (128K x 8) Low Voltage Paged Parallel EEPROMs

Atmel Corporation 

3. Block Diagram

AT28LV010

4. Device Operation

4.1 Read

The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the

data stored at the memory location determined by the address pins is asserted on the outputs.

The outputs are put in the high impedance state when either CE or OE is high. This dual-line

control gives designers flexibility in preventing bus contention in their system.

4.2 Write

The write operation of the AT28LV010 allows 1 to 128 bytes of data to be written into the

device during a single internal programming period. Each write operation must be preceded by

the software data protection (SDP) command sequence. This sequence is a series of three

unique write command operations that enable the internal write circuitry. The command

sequence and the data to be written must conform to the software protected write cycle timing.

Addresses are latched on the falling edge of WE or CE, whichever occurs last and data is

latched on the rising edge of WE or CE, whichever occurs first. Each successive byte must be

written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28LV010

will cease accepting data and commence the internal programming operation. If more than

one data byte is to be written during a single programming operation, they must reside on the

same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition

during the page write operation, A7 - A16 must be the same.

The A0 to A6 inputs are used to specify which bytes within the page are to be written. The

bytes may be loaded in any order and may be altered within the same load period. Only bytes

which are specified for writing will be written; unnecessary cycling of other bytes within the

page does not occur.

3

0395D–PEEPR–10/06

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