74221 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74221

Dual Monostable Multivibrators (with Schmitt Trigger Input)

Fairchild Semiconductor 

Theory of Operation

FIGURE 1.

TRIGGER OPERATION

As shown in Figure 1 and the logic diagram before an input

trigger occurs, the monostable is in the quiescent state with

the Q output LOW, and the timing capacitor CEXT com-

pletely charged to VCC. When the trigger input A goes from

VCC to GND (while inputs B and clear are held to VCC) a

valid trigger is recognized, which turns on comparator C1

and N-channel transistor N11. At the same time the output

latch is set. With transistor N1 on, the capacitor CEXT rap-

idly discharges toward GND until VREF1 is reached. At this

point the output of comparator C1 changes state and tran-

sistor N1 turns off. Comparator C1 then turns off while at

the same time comparator C2 turns on. With transistor N1

off, the capacitor CEXT begins to charge through the timing

resistor, REXT, toward VCC. When the voltage across CEXT

equals VREF2, comparator C2 changes state causing the

output latch to reset (Q goes LOW) while at the same time

disabling comparator C2. This ends the timing cycle with

the monostable in the quiescent state, waiting for the next

trigger.

A valid trigger is also recognized when trigger input B goes

from GND to VCC (while input A is at GND and input clear

is at VCC2). The MM74HC221 can also be triggered when

clear goes from GND to VCC (while A is at Gnd and B is at

VCC6).

It should be noted that in the quiescent state CEXTis fully

charged to VCC causing the current through resistor REXT

to be zero. Both comparators are “off” with the total device

current due only to reverse junction leakages. An added

feature of the MM74HC221 is that the output latch is set via

the input trigger without regard to the capacitor voltage.

Thus, propagation delay from trigger to Q is independent of

the value of CEXT, REXT, or the duty cycle of the input

waveform.

The MM74HC221 is non-retriggerable and will ignore input

transitions on A and B until it has timed out 3 and 4.

RESET OPERATION

These one shots may be reset during the generation of the

output pulse. In the reset mode of operation, an input pulse

on clear sets the reset latch and causes the capacitor to be

fast charged to VCC by turning on transistor Q1 5. When

the voltage on the capacitor reaches VREF2, the reset latch

will clear and then be ready to accept another pulse. If the

clear input is held LOW, any trigger inputs that occur will be

inhibited and the Q and Q outputs of the output latch will

not change. Since the Q output is reset when an input low

level is detected on the Clear input, the output pulse T can

be made significantly shorter than the minimum pulse width

specification.

5

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