74AHCT02PW 데이터 시트보기 (PDF) - NXP Semiconductors.
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74AHCT02PW Datasheet PDF : 13 Pages
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NXP Semiconductors
4. Functional diagram
74AHC02; 74AHCT02
Quad 2-input NOR gate
2 1A
3 1B
5 2A
6 2B
8 3A
9 3B
11 4A
12 4B
1Y 1
2Y 4
3Y 10
4Y 13
mna216
Fig 1. Logic symbol
2
≥1
3
1
5
≥1
6
4
8
≥1
9
10
11
≥1
12
13
001aah084
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna215
Fig 3. Logic diagram (one gate)
1Y 1
1A 2
1B 3
2Y 4
2A 5
2B 6
GND 7
14 VCC
13 4Y
12 4B
02
11 4A
10 3Y
9 3B
8 3A
001aac919
Fig 4. Pin configuration SO14 and TSSOP14
terminal 1
index area
1A 2
1B 3
2Y 4
2A 5
2B 6
02
GND(1)
13 4Y
12 4B
11 4A
10 3Y
9 3B
001aac920
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y
1A
1B
2Y
Pin description
Pin
1
2
3
4
Description
data output
data input
data input
data output
74AHC_AHCT02_3
Product data sheet
Rev. 03 — 7 January 2008
© NXP B.V. 2008. All rights reserved.
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