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74F378 데이터 시트보기 (PDF) - Philips Electronics

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74F378
Philips
Philips Electronics Philips
74F378 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
Philips Semiconductors
Hex D flip-flop with enable
Product specification
74F378
FEATURES
6-bit high-speed parallel register
Positive edge-triggered D-type inputs
Fully buffered common Clock and Enable inputs
Input clamp diodes limit high speed termination effects
Fully TTL and CMOS compatible
DESCRIPTION
The 74F378 has six edge-triggered D-type flip-flops with individual
D inputs and Q outputs. The common buffered Clock (CP) input
loads all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transformed to
the corresponding flop-flop’s Q output. The E input must be stable
one setup time prior to the Low-to-High clock transition for
predictable operation.
PIN CONFIGURATION
TYPE
74F378
TYPICAL fmax
100MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
35mA
ORDERING INFORMATION
DESCRIPTION
16–pin plastic DIP
COMMERCIAL
RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
N74F378N
16–pin plastic SO
N74F378D
PKG DWG #
SOT38-4
SOT109-1
E1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
16 VCC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
SF00927
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
D0 – D5
Data inputs
CP
Clock pulse input (active rising edge)
E
Enable input (active low)
Q0 – Q5
Data outputs
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
74F (U.L.)
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33
LOAD VALUE
HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
1.0mA/20mA
1989 Oct 05
2
853–0067 97804

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