74HCT4052BQ 데이터 시트보기 (PDF) - Philips Electronics

부품명

상세내역

제조사

74HCT4052BQ

Dual 4-channel analog multiplexer/demultiplexer

Philips Electronics 

Philips Semiconductors

Dual 4-channel analog

multiplexer/demultiplexer

Product specification

74HC/HCT4052

FEATURES

• Wide analog input voltage range: ± 5 V.

• Low “ON” resistance:

80 Ω (typ.) at VCC − VEE = 4.5 V

70 Ω (typ.) at VCC − VEE = 6.0 V

60 Ω (typ.) at VCC − VEE = 9.0 V

• Logic level translation:

to enable 5 V logic to communicate

with ± 5 V analog signals

• Typical “break before make” built in

• Output capability: non-standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4052 are high-speed Si-gate CMOS

devices and are pin compatible with the “4052” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT4052 are dual 4-channel analog

multiplexers/demultiplexers with common select logic.

Each multiplexer has four independent inputs/outputs (nY0

to nY3) and a common input/output (nZ). The common

channel select logics include two digital select inputs (S0

and S1) and an active LOW enable input (E).

With E LOW, one of the four switches is selected (low

impedance ON-state) by S0 and S1. With E HIGH, all

switches are in the high impedance OFF-state,

independent of S0 and S1.

VCC and GND are the supply voltage pins for the digital

control inputs (S0 and S1, and E). The VCC to GND ranges

are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT. The

analog inputs/outputs (nY0 to nY3, and nZ) can swing

between VCC as a positive limit and VEE as a negative limit.

VCC − VEE may not exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, VEE is

connected to GND (typically ground).

QUICK REFERENCE DATA

VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL

PARAMETER

CONDITIONS

tPZH/ tPZL

tPHZ/ tPLZ

CI

CPD

CS

turn “ON” time E or Sn to VOS

turn “OFF” time E or Sn to VOS

input capacitance

CL = 15 pF ; RL = 1 kΩ;

VCC = 5 V

power dissipation capacitance per switch notes 1 and 2

max. switch capacitance

independent (Y)

common (Z)

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi +∑ {(CL + CS) × VCC2 × fo)} where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ {(CL +CS) × VCC2 × fo)} = sum of outputs

CL = output load capacitance in pF

CS = max. switch capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

TYPICAL

HC

28

21

3.5

57

HCT

18

13

3.5

57

UNIT

ns

ns

pF

pF

5

5

pF

12

12

pF

December 1990

2

Share Link: