74LS174 데이터 시트보기 (PDF) - ON Semiconductor

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74LS174

Hex D Flip-Flop

ON Semiconductor 

SN74LS174

FUNCTIONAL DESCRIPTION

The LS174 consists of six edge-triggered D flip-flops with

individual D inputs and Q outputs. The Clock (CP) and

Master Reset (MR) are common to all flip-flops.

Each D input’s state is transferred to the corresponding

flip-flop’s output following the LOW to HIGH Clock (CP)

transition.

A LOW input to the Master Reset (MR) will force all

outputs LOW independent of Clock or Data inputs. The

LS174 is useful for applications where the true output only

is required and the Clock and Master Reset are common to

all storage elements.

TRUTH TABLE

Inputs (t = n, MR = H)

Outputs (t = n+1) Note 1

D

Q

H

H

L

L

Note 1: t = n + 1 indicates conditions after next clock.

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min Typ Max Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65 – 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

2.7

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOL

Output LOW Voltage

0.25 0.4

0.35 0.5

V

IOL = 4.0 mA

V

IOL = 8.0 mA

VCC = VCC MIN,

VIN = VIL or VIH

per Truth Table

IIH

Input HIGH Current

20

µA VCC = MAX, VIN = 2.7 V

0.1

mA VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

– 0.4 mA VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

– 20

– 100 mA VCC = MAX

ICC

Power Supply Current

26

mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

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