74LS174 데이터 시트보기 (PDF) - ON Semiconductor
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74LS174 Datasheet PDF : 8 Pages
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SN74LS174
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPHL
tPLH
tPHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
Limits
Min Typ Max
30
40
23
35
20
30
21
30
Unit
MHz
ns
ns
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
th
trec
Parameter
Clock or MR Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max Unit
20
ns
20
ns
5.0
ns
25
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
AC WAVEFORMS
1/fmax
tw
CP
1.3 V
1.3 V
ts(H)
th(H)ts(L)
th(L)
D
*
1.3 V
1.3 V
tPLH
1.3 V
tPHL
Q
1.3 V
1.3 V
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
tW
MR
1.3 V
1.3 V
trec
1.3 V
CP
Q
tPHL
1.3 V
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
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