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74LVC1G175GM 데이터 시트보기 (PDF) - NXP Semiconductors.

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74LVC1G175GM Datasheet PDF : 17 Pages
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
6. Pinning information
6.1 Pinning
74LVC1G175
CP 1
6 MR
GND 2
5 VCC
D3
4Q
001aag506
Fig 4. Pin configuration SOT363
and SOT457
74LVC1G175
CP 1
6 MR
GND 2
5 VCC
D3
4Q
001aag507
Transparent top view
Fig 5. Pin configuration SOT886
74LVC1G175
CP 1
6 MR
GND 2
5 VCC
D3
4Q
001aag508
Transparent top view
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3.
Symbol
CP
GND
D
Q
VCC
MR
Pin description
Pin
1
2
3
4
5
6
Description
clock input (LOW-to-HIGH, edge-triggered)
ground (0 V)
data input
flip-flop output
supply voltage
master reset input (active LOW)
7. Functional description
Table 4. Function table[1]
Operating mode
Input
MR
CP
D
Reset (clear)
L
X
X
Load ‘1’
H
h
Load ‘0’
H
l
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
= LOW-to-HIGH CP transition;
X = don’t care.
Output
Q
L
H
L
74LVC1G175_3
Product data sheet
Rev. 03 — 21 May 2007
© NXP B.V. 2007. All rights reserved.
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