74LVC1G175GV 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC1G175GV Datasheet PDF : 17 Pages
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NXP Semiconductors
74LVC1G175
Single D-type flip-flop with reset; positive-edge trigger
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9.
Symbol Parameter
Conditions
−40 °C to +85 °C
Min Typ[1] Max
th
hold time
D to CP; see Figure 7
VCC = 1.65 V to 1.95 V
0.0
-
-
VCC = 2.3 V to 2.7 V
0.3
-
-
VCC = 2.7 V
0.5
-
-
VCC = 3.0 V to 3.6 V
1.2
0.2
-
VCC = 4.5 V to 5.5 V
0.5
-
-
fmax
maximum
frequency
CP; see Figure 7
VCC = 1.65 V to 1.95 V
80
125
-
VCC = 2.3 V to 2.7 V
175
-
-
VCC = 2.7 V
175
-
-
VCC = 3.0 V to 3.6 V
175 300
-
VCC = 4.5 V to 5.5 V
200
-
-
CPD
power dissipation VI = GND to VCC; VCC = 3.3 V [3]
-
14
-
capacitance
−40 °C to +125 °C Unit
Min
Max
0.0
- ns
0.3
- ns
0.5
- ns
1.2
- ns
0.5
- ns
80
- MHz
175
- MHz
175
- MHz
175
- MHz
200
- MHz
-
- pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
74LVC1G175_3
Product data sheet
Rev. 03 — 21 May 2007
© NXP B.V. 2007. All rights reserved.
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