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74LVC1G80

Single D-type flip-flop; positive-edge trigger

NXP Semiconductors. 

NXP Semiconductors

74LVC1G80

Single D-type flip-flop; positive-edge trigger

7. Functional description

Table 4. Function table[1]

Input

CP

D

↑

L

↑

H

L

X

Output

Q

H

L

q

[1] H = HIGH voltage level;

L = LOW voltage level.

↑ = LOW-to-HIGH CP transition;

X = don’t care;

q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

IIK

input clamping current

VI

input voltage

IOK

output clamping current

VO

output voltage

VI < 0 V

VO > VCC or VO < 0 V

Active mode

Power-down mode

−0.5

−50

[1] −0.5

-

[1][2] −0.5

[1][2] −0.5

+6.5

V

-

mA

+6.5

V

±50

mA

VCC + 0.5 V

+6.5

V

IO

ICC

IGND

Ptot

Tstg

output current

supply current

ground current

total power dissipation

storage temperature

VO = 0 V to VCC

Tamb = −40 °C to +125 °C

-

±50

mA

-

100

mA

−100

-

mA

[3] -

250

mW

−65

+150

°C

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.

For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.

74LVC1G80_8

Product data sheet

Rev. 08 — 29 August 2007

© NXP B.V. 2007. All rights reserved.

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